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authorFabio Estevam <festevam@gmail.com>2012-03-02 05:45:58 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2012-03-07 15:29:57 -0500
commitaa6a9fa1f27414bd099c405bde7c42a3c99078f9 (patch)
treed6fb1a055639fa574d8301410d19d16c849597de /arch/arm/mach-imx
parent192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d (diff)
ARM: mx5: Use common function for configuring AIPS
Now that a common imx_set_aips() function is available, use it on mx51 and mx53. This lets the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c36
-rw-r--r--arch/arm/mach-imx/mm-imx5.c8
2 files changed, 8 insertions, 36 deletions
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a843860..aa15c517d06e 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -149,39 +149,3 @@ int mx50_revision(void)
149 return mx5_cpu_rev; 149 return mx5_cpu_rev;
150} 150}
151EXPORT_SYMBOL(mx50_revision); 151EXPORT_SYMBOL(mx50_revision);
152
153static int __init post_cpu_init(void)
154{
155 unsigned int reg;
156 void __iomem *base;
157
158 if (cpu_is_mx51() || cpu_is_mx53()) {
159 if (cpu_is_mx51())
160 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
161 else
162 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
163
164 __raw_writel(0x0, base + 0x40);
165 __raw_writel(0x0, base + 0x44);
166 __raw_writel(0x0, base + 0x48);
167 __raw_writel(0x0, base + 0x4C);
168 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
169 __raw_writel(reg, base + 0x50);
170
171 if (cpu_is_mx51())
172 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
173 else
174 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
175
176 __raw_writel(0x0, base + 0x40);
177 __raw_writel(0x0, base + 0x44);
178 __raw_writel(0x0, base + 0x48);
179 __raw_writel(0x0, base + 0x4C);
180 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
181 __raw_writel(reg, base + 0x50);
182 }
183
184 return 0;
185}
186
187postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfea3817..93826eb01560 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -191,6 +191,10 @@ void __init imx51_soc_init(void)
191 191
192 /* i.mx51 has the i.mx35 type sdma */ 192 /* i.mx51 has the i.mx35 type sdma */
193 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); 193 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
194
195 /* Setup AIPS registers */
196 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
197 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
194} 198}
195 199
196void __init imx53_soc_init(void) 200void __init imx53_soc_init(void)
@@ -206,4 +210,8 @@ void __init imx53_soc_init(void)
206 210
207 /* i.mx53 has the i.mx35 type sdma */ 211 /* i.mx53 has the i.mx35 type sdma */
208 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); 212 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
213
214 /* Setup AIPS registers */
215 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
216 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
209} 217}