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authorPhilipp Zabel <p.zabel@pengutronix.de>2013-04-17 06:05:58 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-05-12 09:35:22 -0400
commit72cd7447e72a13ce72d760b42ec295430f77300a (patch)
tree265da158ee1454e2f519c63b6324722b95f5e9f6 /arch/arm/mach-imx
parentf722406faae2d073cc1d01063d1123c35425939e (diff)
ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks
The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/ pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 151259003086..ca1717135820 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -177,7 +177,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
177static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; 177static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
178static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; 178static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
179static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; 179static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
180static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", }; 180static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
181static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
181static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 182static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
182static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 183static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
183static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 184static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
@@ -369,8 +370,8 @@ int __init mx6q_clocks_init(void)
369 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 370 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
370 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 371 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
371 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 372 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
372 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 373 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
373 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 374 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
374 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); 375 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
375 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 376 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
376 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 377 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));