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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:04:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:04:39 -0400
commitd0440c59f52d31aa7f74ba8e35cc22ee96acea84 (patch)
tree199470b64cdc30e9f0f7ecd5286ff7cc2e0a969d /arch/arm/mach-imx
parent38eb1dbb0d7d190bdfe2ea824e94dab19e32737f (diff)
parentc4c14f393fe4991a423c21516511ff1011140143 (diff)
Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson: "We've got a fairly large cleanup branch this time. The bulk of this is removal of non-DT platforms of several flavors: - Atmel at91 platforms go full-DT, with removal of remaining board-file based support - OMAP removes legacy board files for three more platforms - removal of non-DT mach-msm, newer Qualcomm platforms now live in mach-qcom - Freescale i.MX25 also removes non-DT platform support" Most of the rest of the changes here are fallout from the above, i.e. for example removal of drivers that now lack platforms, etc. * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (58 commits) mmc: Remove msm_sdcc driver gpio: Remove gpio-msm-v1 driver ARM: Remove mach-msm and associated ARM architecture code ARM: shmobile: cpuidle: Remove the pointless default driver ARM: davinci: dm646x: Add interrupt resource for McASPs ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x ARM: davinci: dm646x: Clean up the McASP DMA resources ARM: davinci: devices-da8xx: Add support for McASP2 on da830 ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request ARM: OMAP2+: Remove legacy support for omap3 TouchBook ARM: OMAP3: Remove legacy support for devkit8000 ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board ARM: shmobile: Consolidate the pm code for R-Car Gen2 ARM: shmobile: r8a7791: Correct SYSCIER value ARM: shmobile: r8a7790: Correct SYSCIER value ARM: at91: remove old setup ARM: at91: sama5d4: remove useless map_io ARM: at91: sama5 use SoC detection infrastructure ...
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/Kconfig81
-rw-r--r--arch/arm/mach-imx/Makefile8
-rw-r--r--arch/arm/mach-imx/clk-imx25.c75
-rw-r--r--arch/arm/mach-imx/common.h5
-rw-r--r--arch/arm/mach-imx/cpu-imx25.c11
-rw-r--r--arch/arm/mach-imx/devices-imx25.h85
-rw-r--r--arch/arm/mach-imx/devices/Kconfig3
-rw-r--r--arch/arm/mach-imx/devices/Makefile1
-rw-r--r--arch/arm/mach-imx/devices/platform-fec.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-fb.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-i2c.c10
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-keypad.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-ssi.c9
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-uart.c12
-rw-r--r--arch/arm/mach-imx/devices/platform-imx2-wdt.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imxdi_rtc.c42
-rw-r--r--arch/arm/mach-imx/devices/platform-mx2-camera.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-mxc-ehci.c7
-rw-r--r--arch/arm/mach-imx/devices/platform-mxc_nand.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-spi_imx.c11
-rw-r--r--arch/arm/mach-imx/ehci-imx25.c99
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c310
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c2
-rw-r--r--arch/arm/mach-imx/hardware.h1
-rw-r--r--arch/arm/mach-imx/iomux-mx25.h524
-rw-r--r--arch/arm/mach-imx/iomux-mx3.h2
-rw-r--r--arch/arm/mach-imx/iomux-v3.c5
-rw-r--r--arch/arm/mach-imx/iomux-v3.h5
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c2
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c172
-rw-r--r--arch/arm/mach-imx/mach-imx25.c (renamed from arch/arm/mach-imx/imx25-dt.c)20
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c270
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c2
-rw-r--r--arch/arm/mach-imx/mach-vpr200.c2
-rw-r--r--arch/arm/mach-imx/mm-imx25.c89
-rw-r--r--arch/arm/mach-imx/mx25.h117
38 files changed, 57 insertions, 1962 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c8dffcee9736..0748747b2bc6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -77,13 +77,6 @@ config SOC_IMX21
77 select IMX_HAVE_IOMUX_V1 77 select IMX_HAVE_IOMUX_V1
78 select MXC_AVIC 78 select MXC_AVIC
79 79
80config SOC_IMX25
81 bool
82 select ARCH_MXC_IOMUX_V3
83 select CPU_ARM926T
84 select MXC_AVIC
85 select PINCTRL_IMX25
86
87config SOC_IMX27 80config SOC_IMX27
88 bool 81 bool
89 select CPU_ARM926T 82 select CPU_ARM926T
@@ -149,62 +142,6 @@ config MACH_MX21ADS
149 Include support for MX21ADS platform. This includes specific 142 Include support for MX21ADS platform. This includes specific
150 configurations for the board and its peripherals. 143 configurations for the board and its peripherals.
151 144
152comment "MX25 platforms:"
153
154config MACH_MX25_3DS
155 bool "Support MX25PDK (3DS) Platform"
156 select IMX_HAVE_PLATFORM_FLEXCAN
157 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
158 select IMX_HAVE_PLATFORM_IMX2_WDT
159 select IMX_HAVE_PLATFORM_IMXDI_RTC
160 select IMX_HAVE_PLATFORM_IMX_FB
161 select IMX_HAVE_PLATFORM_IMX_I2C
162 select IMX_HAVE_PLATFORM_IMX_KEYPAD
163 select IMX_HAVE_PLATFORM_IMX_UART
164 select IMX_HAVE_PLATFORM_MXC_EHCI
165 select IMX_HAVE_PLATFORM_MXC_NAND
166 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
167 select SOC_IMX25
168
169config MACH_EUKREA_CPUIMX25SD
170 bool "Support Eukrea CPUIMX25 Platform"
171 select IMX_HAVE_PLATFORM_FLEXCAN
172 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
173 select IMX_HAVE_PLATFORM_IMX2_WDT
174 select IMX_HAVE_PLATFORM_IMXDI_RTC
175 select IMX_HAVE_PLATFORM_IMX_FB
176 select IMX_HAVE_PLATFORM_IMX_I2C
177 select IMX_HAVE_PLATFORM_IMX_UART
178 select IMX_HAVE_PLATFORM_MXC_EHCI
179 select IMX_HAVE_PLATFORM_MXC_NAND
180 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
181 select USB_ULPI_VIEWPORT if USB_ULPI
182 select SOC_IMX25
183
184choice
185 prompt "Baseboard"
186 depends on MACH_EUKREA_CPUIMX25SD
187 default MACH_EUKREA_MBIMXSD25_BASEBOARD
188
189config MACH_EUKREA_MBIMXSD25_BASEBOARD
190 bool "Eukrea MBIMXSD development board"
191 select IMX_HAVE_PLATFORM_GPIO_KEYS
192 select IMX_HAVE_PLATFORM_IMX_SSI
193 select IMX_HAVE_PLATFORM_SPI_IMX
194 select LEDS_GPIO_REGISTER
195 help
196 This adds board specific devices that can be found on Eukrea's
197 MBIMXSD evaluation board.
198
199endchoice
200
201config MACH_IMX25_DT
202 bool "Support i.MX25 platforms from device tree"
203 select SOC_IMX25
204 help
205 Include support for Freescale i.MX25 based platforms
206 using the device tree for discovery
207
208comment "MX27 platforms:" 145comment "MX27 platforms:"
209 146
210config MACH_MX27ADS 147config MACH_MX27ADS
@@ -557,6 +494,20 @@ config MACH_VPR200
557 494
558endif 495endif
559 496
497if ARCH_MULTI_V5
498
499comment "Device tree only"
500
501config SOC_IMX25
502 bool "i.MX25 support"
503 select ARCH_MXC_IOMUX_V3
504 select CPU_ARM926T
505 select MXC_AVIC
506 select PINCTRL_IMX25
507 help
508 This enables support for Freescale i.MX25 processor
509endif
510
560if ARCH_MULTI_V7 511if ARCH_MULTI_V7
561 512
562comment "Device tree only" 513comment "Device tree only"
@@ -637,7 +588,7 @@ config SOC_VF610
637 select PL310_ERRATA_769419 if CACHE_L2X0 588 select PL310_ERRATA_769419 if CACHE_L2X0
638 589
639 help 590 help
640 This enable support for Freescale Vybrid VF610 processor. 591 This enables support for Freescale Vybrid VF610 processor.
641 592
642choice 593choice
643 prompt "Clocksource for scheduler clock" 594 prompt "Clocksource for scheduler clock"
@@ -667,7 +618,7 @@ config SOC_LS1021A
667 select ZONE_DMA if ARM_LPAE 618 select ZONE_DMA if ARM_LPAE
668 619
669 help 620 help
670 This enable support for Freescale LS1021A processor. 621 This enables support for Freescale LS1021A processor.
671 622
672endif 623endif
673 624
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8d1b10180908..3244cf1d2773 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o
3obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o 3obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
4obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o 4obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
5 5
6obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o 6obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
7 7
8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o 8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
9obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o 9obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
@@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
48# i.MX21 based machines 48# i.MX21 based machines
49obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 49obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
50 50
51# i.MX25 based machines
52obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
53obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
54obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
55obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
56
57# i.MX27 based machines 51# i.MX27 based machines
58obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 52obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
59obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o 53obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 59c0c8558c6b..9c2633a9de9f 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -30,7 +30,6 @@
30#include "clk.h" 30#include "clk.h"
31#include "common.h" 31#include "common.h"
32#include "hardware.h" 32#include "hardware.h"
33#include "mx25.h"
34 33
35#define CCM_MPCTL 0x00 34#define CCM_MPCTL 0x00
36#define CCM_UPCTL 0x04 35#define CCM_UPCTL 0x04
@@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
239 return 0; 238 return 0;
240} 239}
241 240
242int __init mx25_clocks_init(void)
243{
244 void __iomem *ccm;
245
246 ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
247
248 __mx25_clocks_init(24000000, ccm);
249
250 clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
251 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
252 /* i.mx25 has the i.mx21 type uart */
253 clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
254 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
255 clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
256 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
257 clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
258 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
259 clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
260 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
261 clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
262 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
263 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
264 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
265 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
266 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
267 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
268 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
269 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
270 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
271 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
272 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
273 clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
274 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
275 clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
276 /* i.mx25 has the i.mx35 type cspi */
277 clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
278 clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
279 clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
280 clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
281 clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
282 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
283 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
284 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
285 clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
286 clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
287 clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
288 clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
289 clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
290 clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
291 clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
292 clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
293 clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
294 clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
295 clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
296 clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
297 clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
298 clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
299 clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
300 clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
301 clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
302 clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
303 clk_register_clkdev(clk[dummy], "audmux", NULL);
304 clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
305 clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
306 /* i.mx25 has the i.mx35 type sdma */
307 clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
308 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
309 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
310
311 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
312
313 return 0;
314}
315
316static void __init mx25_clocks_init_dt(struct device_node *np) 241static void __init mx25_clocks_init_dt(struct device_node *np)
317{ 242{
318 struct device_node *refnp; 243 struct device_node *refnp;
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1028b6c505c4..771ecfe96c14 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -23,13 +23,11 @@ struct of_device_id;
23 23
24void mx1_map_io(void); 24void mx1_map_io(void);
25void mx21_map_io(void); 25void mx21_map_io(void);
26void mx25_map_io(void);
27void mx27_map_io(void); 26void mx27_map_io(void);
28void mx31_map_io(void); 27void mx31_map_io(void);
29void mx35_map_io(void); 28void mx35_map_io(void);
30void imx1_init_early(void); 29void imx1_init_early(void);
31void imx21_init_early(void); 30void imx21_init_early(void);
32void imx25_init_early(void);
33void imx27_init_early(void); 31void imx27_init_early(void);
34void imx31_init_early(void); 32void imx31_init_early(void);
35void imx35_init_early(void); 33void imx35_init_early(void);
@@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *);
37void tzic_init_irq(void); 35void tzic_init_irq(void);
38void mx1_init_irq(void); 36void mx1_init_irq(void);
39void mx21_init_irq(void); 37void mx21_init_irq(void);
40void mx25_init_irq(void);
41void mx27_init_irq(void); 38void mx27_init_irq(void);
42void mx31_init_irq(void); 39void mx31_init_irq(void);
43void mx35_init_irq(void); 40void mx35_init_irq(void);
44void imx1_soc_init(void); 41void imx1_soc_init(void);
45void imx21_soc_init(void); 42void imx21_soc_init(void);
46void imx25_soc_init(void);
47void imx27_soc_init(void); 43void imx27_soc_init(void);
48void imx31_soc_init(void); 44void imx31_soc_init(void);
49void imx35_soc_init(void); 45void imx35_soc_init(void);
@@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq);
51void mxc_timer_init(void __iomem *, int); 47void mxc_timer_init(void __iomem *, int);
52int mx1_clocks_init(unsigned long fref); 48int mx1_clocks_init(unsigned long fref);
53int mx21_clocks_init(unsigned long lref, unsigned long fref); 49int mx21_clocks_init(unsigned long lref, unsigned long fref);
54int mx25_clocks_init(void);
55int mx27_clocks_init(unsigned long fref); 50int mx27_clocks_init(unsigned long fref);
56int mx31_clocks_init(unsigned long fref); 51int mx31_clocks_init(unsigned long fref);
57int mx35_clocks_init(void); 52int mx35_clocks_init(void);
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index 96ec64b5ff7d..d0ad67e802d3 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -11,6 +11,8 @@
11 */ 11 */
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
14 16
15#include "iim.h" 17#include "iim.h"
16#include "hardware.h" 18#include "hardware.h"
@@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1;
20static int mx25_read_cpu_rev(void) 22static int mx25_read_cpu_rev(void)
21{ 23{
22 u32 rev; 24 u32 rev;
25 void __iomem *iim_base;
26 struct device_node *np;
27
28 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
29 iim_base = of_iomap(np, 0);
30 BUG_ON(!iim_base);
31 rev = readl(iim_base + MXC_IIMSREV);
32 iounmap(iim_base);
23 33
24 rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
25 switch (rev) { 34 switch (rev) {
26 case 0x00: 35 case 0x00:
27 return IMX_CHIP_REVISION_1_0; 36 return IMX_CHIP_REVISION_1_0;
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
deleted file mode 100644
index 61a114cddc39..000000000000
--- a/arch/arm/mach-imx/devices-imx25.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include "devices/devices-common.h"
10
11extern const struct imx_fec_data imx25_fec_data;
12#define imx25_add_fec(pdata) \
13 imx_add_fec(&imx25_fec_data, pdata)
14
15extern const struct imx_flexcan_data imx25_flexcan_data[];
16#define imx25_add_flexcan(id) \
17 imx_add_flexcan(&imx25_flexcan_data[id])
18#define imx25_add_flexcan0() imx25_add_flexcan(0)
19#define imx25_add_flexcan1() imx25_add_flexcan(1)
20
21extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
22#define imx25_add_fsl_usb2_udc(pdata) \
23 imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
24
25extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
26#define imx25_add_imxdi_rtc() \
27 imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
28
29extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
30#define imx25_add_imx2_wdt() \
31 imx_add_imx2_wdt(&imx25_imx2_wdt_data)
32
33extern const struct imx_imx_fb_data imx25_imx_fb_data;
34#define imx25_add_imx_fb(pdata) \
35 imx_add_imx_fb(&imx25_imx_fb_data, pdata)
36
37extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
38#define imx25_add_imx_i2c(id, pdata) \
39 imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
40#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
41#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
42#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
43
44extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
45#define imx25_add_imx_keypad(pdata) \
46 imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
47
48extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
49#define imx25_add_imx_ssi(id, pdata) \
50 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
51
52extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
53#define imx25_add_imx_uart(id, pdata) \
54 imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
55#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
56#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata)
57#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata)
58#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
59#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
60
61extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
62#define imx25_add_mx2_camera(pdata) \
63 imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
64
65extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
66#define imx25_add_mxc_ehci_otg(pdata) \
67 imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
68extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
69#define imx25_add_mxc_ehci_hs(pdata) \
70 imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
71
72extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
73#define imx25_add_mxc_nand(pdata) \
74 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
75
76extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
77#define imx25_add_sdhci_esdhc_imx(id, pdata) \
78 imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
79
80extern const struct imx_spi_imx_data imx25_cspi_data[];
81#define imx25_add_spi_imx(id, pdata) \
82 imx_add_spi_imx(&imx25_cspi_data[id], pdata)
83#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
84#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
85#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 1d2cc1805f3e..3a552989248e 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
21config IMX_HAVE_PLATFORM_IMX2_WDT 21config IMX_HAVE_PLATFORM_IMX2_WDT
22 bool 22 bool
23 23
24config IMX_HAVE_PLATFORM_IMXDI_RTC
25 bool
26
27config IMX_HAVE_PLATFORM_IMX_FB 24config IMX_HAVE_PLATFORM_IMX_FB
28 bool 25 bool
29 26
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 8fdb12b4ca7e..e5cf587bc1a0 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o
8obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o 8obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
9obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o 9obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o 10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
11obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
12obj-y += platform-imx-dma.o 11obj-y += platform-imx-dma.o
13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o 12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o 13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index d86f9250b4ee..b403a4fe2892 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -19,11 +19,6 @@
19 .irq = soc ## _INT_FEC, \ 19 .irq = soc ## _INT_FEC, \
20 } 20 }
21 21
22#ifdef CONFIG_SOC_IMX25
23const struct imx_fec_data imx25_fec_data __initconst =
24 imx_fec_data_entry_single(MX25, "imx25-fec");
25#endif /* ifdef CONFIG_SOC_IMX25 */
26
27#ifdef CONFIG_SOC_IMX27 22#ifdef CONFIG_SOC_IMX27
28const struct imx_fec_data imx27_fec_data __initconst = 23const struct imx_fec_data imx27_fec_data __initconst =
29 imx_fec_data_entry_single(MX27, "imx27-fec"); 24 imx_fec_data_entry_single(MX27, "imx27-fec");
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 23b0061347cb..25e1de6f3a47 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -18,11 +18,6 @@
18 .irq = soc ## _INT_USB_OTG, \ 18 .irq = soc ## _INT_USB_OTG, \
19 } 19 }
20 20
21#ifdef CONFIG_SOC_IMX25
22const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
23 imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
24#endif /* ifdef CONFIG_SOC_IMX25 */
25
26#ifdef CONFIG_SOC_IMX27 21#ifdef CONFIG_SOC_IMX27
27const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = 22const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
28 imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27"); 23 imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 25a47c616b2d..7df6328306f9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
29 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); 29 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
30#endif /* ifdef CONFIG_SOC_IMX21 */ 30#endif /* ifdef CONFIG_SOC_IMX21 */
31 31
32#ifdef CONFIG_SOC_IMX25
33const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
34 imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
35#endif /* ifdef CONFIG_SOC_IMX25 */
36
37#ifdef CONFIG_SOC_IMX27 32#ifdef CONFIG_SOC_IMX27
38const struct imx_imx_fb_data imx27_imx_fb_data __initconst = 33const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
39 imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K); 34 imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 644ac2689882..ae9791522fc8 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
31 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); 31 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX21 */ 32#endif /* ifdef CONFIG_SOC_IMX21 */
33 33
34#ifdef CONFIG_SOC_IMX25
35const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
36#define imx25_imx_i2c_data_entry(_id, _hwid) \
37 imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
38 imx25_imx_i2c_data_entry(0, 1),
39 imx25_imx_i2c_data_entry(1, 2),
40 imx25_imx_i2c_data_entry(2, 3),
41};
42#endif /* ifdef CONFIG_SOC_IMX25 */
43
44#ifdef CONFIG_SOC_IMX27 34#ifdef CONFIG_SOC_IMX27
45const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { 35const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
46#define imx27_imx_i2c_data_entry(_id, _hwid) \ 36#define imx27_imx_i2c_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index f42200b7aca9..479e4d70dbf9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
21 imx_imx_keypad_data_entry_single(MX21, SZ_16); 21 imx_imx_keypad_data_entry_single(MX21, SZ_16);
22#endif /* ifdef CONFIG_SOC_IMX21 */ 22#endif /* ifdef CONFIG_SOC_IMX21 */
23 23
24#ifdef CONFIG_SOC_IMX25
25const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
26 imx_imx_keypad_data_entry_single(MX25, SZ_16K);
27#endif /* ifdef CONFIG_SOC_IMX25 */
28
29#ifdef CONFIG_SOC_IMX27 24#ifdef CONFIG_SOC_IMX27
30const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = 25const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
31 imx_imx_keypad_data_entry_single(MX27, SZ_16); 26 imx_imx_keypad_data_entry_single(MX27, SZ_16);
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index 1c7c721ebff1..6f0e94eb29ee 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
30}; 30};
31#endif /* ifdef CONFIG_SOC_IMX21 */ 31#endif /* ifdef CONFIG_SOC_IMX21 */
32 32
33#ifdef CONFIG_SOC_IMX25
34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
35#define imx25_imx_ssi_data_entry(_id, _hwid) \
36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
37 imx25_imx_ssi_data_entry(0, 1),
38 imx25_imx_ssi_data_entry(1, 2),
39};
40#endif /* ifdef CONFIG_SOC_IMX25 */
41
42#ifdef CONFIG_SOC_IMX27 33#ifdef CONFIG_SOC_IMX27
43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { 34const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
44#define imx27_imx_ssi_data_entry(_id, _hwid) \ 35#define imx27_imx_ssi_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 8c01836bc1d4..6962cff4a950 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
47}; 47};
48#endif 48#endif
49 49
50#ifdef CONFIG_SOC_IMX25
51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
52#define imx25_imx_uart_data_entry(_id, _hwid) \
53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
54 imx25_imx_uart_data_entry(0, 1),
55 imx25_imx_uart_data_entry(1, 2),
56 imx25_imx_uart_data_entry(2, 3),
57 imx25_imx_uart_data_entry(3, 4),
58 imx25_imx_uart_data_entry(4, 5),
59};
60#endif /* ifdef CONFIG_SOC_IMX25 */
61
62#ifdef CONFIG_SOC_IMX27 50#ifdef CONFIG_SOC_IMX27
63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { 51const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
64#define imx27_imx_uart_data_entry(_id, _hwid) \ 52#define imx27_imx_uart_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 54f63bc25ca4..8c134c8d7500 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
25 imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); 25 imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
26#endif /* ifdef CONFIG_SOC_IMX21 */ 26#endif /* ifdef CONFIG_SOC_IMX21 */
27 27
28#ifdef CONFIG_SOC_IMX25
29const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
30 imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
31#endif /* ifdef CONFIG_SOC_IMX25 */
32
33#ifdef CONFIG_SOC_IMX27 28#ifdef CONFIG_SOC_IMX27
34const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = 29const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
35 imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); 30 imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
deleted file mode 100644
index 5bb490d556ea..000000000000
--- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10
11#include "../hardware.h"
12#include "devices-common.h"
13
14#define imx_imxdi_rtc_data_entry_single(soc) \
15 { \
16 .iobase = soc ## _DRYICE_BASE_ADDR, \
17 .irq = soc ## _INT_DRYICE, \
18 }
19
20#ifdef CONFIG_SOC_IMX25
21const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
22 imx_imxdi_rtc_data_entry_single(MX25);
23#endif /* ifdef CONFIG_SOC_IMX25 */
24
25struct platform_device *__init imx_add_imxdi_rtc(
26 const struct imx_imxdi_rtc_data *data)
27{
28 struct resource res[] = {
29 {
30 .start = data->iobase,
31 .end = data->iobase + SZ_16K - 1,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = data->irq,
35 .end = data->irq,
36 .flags = IORESOURCE_IRQ,
37 },
38 };
39
40 return imx_add_platform_device("imxdi_rtc", 0,
41 res, ARRAY_SIZE(res), NULL, 0);
42}
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index b53e1f348f51..4c377c33242c 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -27,11 +27,6 @@
27 .irqemmaprp = soc ## _INT_EMMAPRP, \ 27 .irqemmaprp = soc ## _INT_EMMAPRP, \
28 } 28 }
29 29
30#ifdef CONFIG_SOC_IMX25
31const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
32 imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
33#endif /* ifdef CONFIG_SOC_IMX25 */
34
35#ifdef CONFIG_SOC_IMX27 30#ifdef CONFIG_SOC_IMX27
36const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = 31const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
37 imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera"); 32 imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 296353662ff0..4537abd2a8f2 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -18,13 +18,6 @@
18 .irq = soc ## _INT_USB_ ## hs, \ 18 .irq = soc ## _INT_USB_ ## hs, \
19 } 19 }
20 20
21#ifdef CONFIG_SOC_IMX25
22const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
23 imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
24const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
25 imx_mxc_ehci_data_entry_single(MX25, 1, HS);
26#endif /* ifdef CONFIG_SOC_IMX25 */
27
28#ifdef CONFIG_SOC_IMX27 21#ifdef CONFIG_SOC_IMX27
29const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = 22const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
30 imx_mxc_ehci_data_entry_single(MX27, 0, OTG); 23 imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index fa618a34f462..676df4920c7b 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
34 imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K); 34 imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
35#endif /* ifdef CONFIG_SOC_IMX21 */ 35#endif /* ifdef CONFIG_SOC_IMX21 */
36 36
37#ifdef CONFIG_SOC_IMX25
38const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
39 imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
40#endif /* ifdef CONFIG_SOC_IMX25 */
41
42#ifdef CONFIG_SOC_IMX27 37#ifdef CONFIG_SOC_IMX27
43const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = 38const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
44 imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K); 39 imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index aca825d74c48..5e9707b47f92 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
39}; 39};
40#endif 40#endif
41 41
42#ifdef CONFIG_SOC_IMX25
43/* i.mx25 has the i.mx35 type cspi */
44const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
45#define imx25_cspi_data_entry(_id, _hwid) \
46 imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
47 imx25_cspi_data_entry(0, 1),
48 imx25_cspi_data_entry(1, 2),
49 imx25_cspi_data_entry(2, 3),
50};
51#endif /* ifdef CONFIG_SOC_IMX25 */
52
53#ifdef CONFIG_SOC_IMX27 42#ifdef CONFIG_SOC_IMX27
54const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { 43const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
55#define imx27_cspi_data_entry(_id, _hwid) \ 44#define imx27_cspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
deleted file mode 100644
index 42a5a3d14c5f..000000000000
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/platform_data/usb-ehci-mxc.h>
19
20#include "ehci.h"
21#include "hardware.h"
22
23#define USBCTRL_OTGBASE_OFFSET 0x600
24
25#define MX25_OTG_SIC_SHIFT 29
26#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
27#define MX25_OTG_PM_BIT (1 << 24)
28#define MX25_OTG_PP_BIT (1 << 11)
29#define MX25_OTG_OCPOL_BIT (1 << 3)
30
31#define MX25_H1_SIC_SHIFT 21
32#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
33#define MX25_H1_PP_BIT (1 << 18)
34#define MX25_H1_PM_BIT (1 << 16)
35#define MX25_H1_IPPUE_UP_BIT (1 << 7)
36#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
37#define MX25_H1_TLL_BIT (1 << 5)
38#define MX25_H1_USBTE_BIT (1 << 4)
39#define MX25_H1_OCPOL_BIT (1 << 2)
40
41int mx25_initialize_usb_hw(int port, unsigned int flags)
42{
43 unsigned int v;
44
45 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
46
47 switch (port) {
48 case 0: /* OTG port */
49 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
50 MX25_OTG_OCPOL_BIT);
51 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
52
53 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
54 v |= MX25_OTG_PM_BIT;
55
56 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
57 v |= MX25_OTG_PP_BIT;
58
59 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
60 v |= MX25_OTG_OCPOL_BIT;
61
62 break;
63 case 1: /* H1 port */
64 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
65 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
66 MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
67 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
68
69 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
70 v |= MX25_H1_PM_BIT;
71
72 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
73 v |= MX25_H1_PP_BIT;
74
75 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
76 v |= MX25_H1_OCPOL_BIT;
77
78 if (!(flags & MXC_EHCI_TTL_ENABLED))
79 v |= MX25_H1_TLL_BIT;
80
81 if (flags & MXC_EHCI_INTERNAL_PHY)
82 v |= MX25_H1_USBTE_BIT;
83
84 if (flags & MXC_EHCI_IPPUE_DOWN)
85 v |= MX25_H1_IPPUE_DOWN_BIT;
86
87 if (flags & MXC_EHCI_IPPUE_UP)
88 v |= MX25_H1_IPPUE_UP_BIT;
89
90 break;
91 default:
92 return -EINVAL;
93 }
94
95 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
96
97 return 0;
98}
99
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
deleted file mode 100644
index e77cc3af6db2..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ /dev/null
@@ -1,310 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/input.h>
26#include <linux/spi/spi.h>
27#include <video/platform_lcd.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#include "common.h"
33#include "devices-imx25.h"
34#include "hardware.h"
35#include "iomux-mx25.h"
36#include "mx25.h"
37
38static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
39 /* LCD */
40 MX25_PAD_LD0__LD0,
41 MX25_PAD_LD1__LD1,
42 MX25_PAD_LD2__LD2,
43 MX25_PAD_LD3__LD3,
44 MX25_PAD_LD4__LD4,
45 MX25_PAD_LD5__LD5,
46 MX25_PAD_LD6__LD6,
47 MX25_PAD_LD7__LD7,
48 MX25_PAD_LD8__LD8,
49 MX25_PAD_LD9__LD9,
50 MX25_PAD_LD10__LD10,
51 MX25_PAD_LD11__LD11,
52 MX25_PAD_LD12__LD12,
53 MX25_PAD_LD13__LD13,
54 MX25_PAD_LD14__LD14,
55 MX25_PAD_LD15__LD15,
56 MX25_PAD_GPIO_E__LD16,
57 MX25_PAD_GPIO_F__LD17,
58 MX25_PAD_HSYNC__HSYNC,
59 MX25_PAD_VSYNC__VSYNC,
60 MX25_PAD_LSCLK__LSCLK,
61 MX25_PAD_OE_ACD__OE_ACD,
62 MX25_PAD_CONTRAST__CONTRAST,
63 /* LCD_PWR */
64 MX25_PAD_PWM__GPIO_1_26,
65 /* LED */
66 MX25_PAD_POWER_FAIL__GPIO_3_19,
67 /* SWITCH */
68 MX25_PAD_VSTBY_ACK__GPIO_3_18,
69 /* UART2 */
70 MX25_PAD_UART2_RTS__UART2_RTS,
71 MX25_PAD_UART2_CTS__UART2_CTS,
72 MX25_PAD_UART2_TXD__UART2_TXD,
73 MX25_PAD_UART2_RXD__UART2_RXD,
74 /* SD1 */
75 MX25_PAD_SD1_CMD__SD1_CMD,
76 MX25_PAD_SD1_CLK__SD1_CLK,
77 MX25_PAD_SD1_DATA0__SD1_DATA0,
78 MX25_PAD_SD1_DATA1__SD1_DATA1,
79 MX25_PAD_SD1_DATA2__SD1_DATA2,
80 MX25_PAD_SD1_DATA3__SD1_DATA3,
81 /* SD1 CD */
82 MX25_PAD_DE_B__GPIO_2_20,
83 /* I2S */
84 MX25_PAD_KPP_COL3__AUD5_TXFS,
85 MX25_PAD_KPP_COL2__AUD5_TXC,
86 MX25_PAD_KPP_COL1__AUD5_RXD,
87 MX25_PAD_KPP_COL0__AUD5_TXD,
88 /* CAN */
89 MX25_PAD_GPIO_D__CAN2_RX,
90 MX25_PAD_GPIO_C__CAN2_TX,
91 /* SPI1 */
92 MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
93 MX25_PAD_CSPI1_MISO__CSPI1_MISO,
94 MX25_PAD_CSPI1_SS0__GPIO_1_16,
95 MX25_PAD_CSPI1_SS1__GPIO_1_17,
96 MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
97 MX25_PAD_CSPI1_RDY__GPIO_2_22,
98};
99
100#define GPIO_LED1 IMX_GPIO_NR(3, 19)
101#define GPIO_SWITCH1 IMX_GPIO_NR(3, 18)
102#define GPIO_SD1CD IMX_GPIO_NR(2, 20)
103#define GPIO_LCDPWR IMX_GPIO_NR(1, 26)
104#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 16)
105#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 17)
106#define GPIO_SPI1_IRQ IMX_GPIO_NR(2, 22)
107
108static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
109 {
110 .mode = {
111 .name = "CMO-QVGA",
112 .refresh = 60,
113 .xres = 320,
114 .yres = 240,
115 .pixclock = KHZ2PICOS(6500),
116 .left_margin = 30,
117 .right_margin = 38,
118 .upper_margin = 20,
119 .lower_margin = 3,
120 .hsync_len = 15,
121 .vsync_len = 4,
122 },
123 .bpp = 16,
124 .pcr = 0xCAD08B80,
125 }, {
126 .mode = {
127 .name = "DVI-VGA",
128 .refresh = 60,
129 .xres = 640,
130 .yres = 480,
131 .pixclock = 32000,
132 .hsync_len = 7,
133 .left_margin = 100,
134 .right_margin = 100,
135 .vsync_len = 7,
136 .upper_margin = 7,
137 .lower_margin = 100,
138 },
139 .pcr = 0xFA208B80,
140 .bpp = 16,
141 }, {
142 .mode = {
143 .name = "DVI-SVGA",
144 .refresh = 60,
145 .xres = 800,
146 .yres = 600,
147 .pixclock = 25000,
148 .hsync_len = 7,
149 .left_margin = 75,
150 .right_margin = 75,
151 .vsync_len = 7,
152 .upper_margin = 7,
153 .lower_margin = 75,
154 },
155 .pcr = 0xFA208B80,
156 .bpp = 16,
157 },
158};
159
160static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
161 .mode = eukrea_mximxsd_modes,
162 .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
163 .pwmr = 0x00A903FF,
164 .lscr1 = 0x00120300,
165 .dmacr = 0x00040060,
166};
167
168static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
169 unsigned int power)
170{
171 if (power)
172 gpio_direction_output(GPIO_LCDPWR, 1);
173 else
174 gpio_direction_output(GPIO_LCDPWR, 0);
175}
176
177static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
178 .set_power = eukrea_mbimxsd_lcd_power_set,
179};
180
181static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
182 .name = "platform-lcd",
183 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
184};
185
186static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
187 {
188 .name = "led1",
189 .default_trigger = "heartbeat",
190 .active_low = 1,
191 .gpio = GPIO_LED1,
192 },
193};
194
195static const struct gpio_led_platform_data
196 eukrea_mbimxsd_led_info __initconst = {
197 .leds = eukrea_mbimxsd_leds,
198 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
199};
200
201static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
202 {
203 .gpio = GPIO_SWITCH1,
204 .code = BTN_0,
205 .desc = "BP1",
206 .active_low = 1,
207 .wakeup = 1,
208 },
209};
210
211static const struct gpio_keys_platform_data
212 eukrea_mbimxsd_button_data __initconst = {
213 .buttons = eukrea_mbimxsd_gpio_buttons,
214 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
215};
216
217static struct platform_device *platform_devices[] __initdata = {
218 &eukrea_mbimxsd_lcd_powerdev,
219};
220
221static const struct imxuart_platform_data uart_pdata __initconst = {
222 .flags = IMXUART_HAVE_RTSCTS,
223};
224
225static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
226 {
227 I2C_BOARD_INFO("tlv320aic23", 0x1a),
228 },
229};
230
231static const
232struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
233 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
234};
235
236static struct esdhc_platform_data sd1_pdata = {
237 .cd_gpio = GPIO_SD1CD,
238 .cd_type = ESDHC_CD_GPIO,
239 .wp_type = ESDHC_WP_NONE,
240};
241
242static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
243 {
244 .modalias = "spidev",
245 .max_speed_hz = 20000000,
246 .bus_num = 0,
247 .chip_select = 0,
248 .mode = SPI_MODE_0,
249 },
250 {
251 .modalias = "spidev",
252 .max_speed_hz = 20000000,
253 .bus_num = 0,
254 .chip_select = 1,
255 .mode = SPI_MODE_0,
256 },
257};
258
259static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
260
261static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
262 .chipselect = eukrea_mbimxsd25_spi_cs,
263 .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
264};
265
266/*
267 * system init for baseboard usage. Will be called by cpuimx25 init.
268 *
269 * Add platform devices present on this baseboard and init
270 * them from CPU side as far as required to use them later on
271 */
272void __init eukrea_mbimxsd25_baseboard_init(void)
273{
274 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
275 ARRAY_SIZE(eukrea_mbimxsd_pads)))
276 printk(KERN_ERR "error setting mbimxsd pads !\n");
277
278 imx25_add_imx_uart1(&uart_pdata);
279 imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
280 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
281
282 imx25_add_flexcan1();
283 imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
284
285 gpio_request(GPIO_LED1, "LED1");
286 gpio_direction_output(GPIO_LED1, 1);
287 gpio_free(GPIO_LED1);
288
289 gpio_request(GPIO_SWITCH1, "SWITCH1");
290 gpio_direction_input(GPIO_SWITCH1);
291 gpio_free(GPIO_SWITCH1);
292
293 gpio_request(GPIO_LCDPWR, "LCDPWR");
294 gpio_direction_output(GPIO_LCDPWR, 1);
295
296 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
297 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
298
299 gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
300 gpio_direction_input(GPIO_SPI1_IRQ);
301 gpio_free(GPIO_SPI1_IRQ);
302 imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
303 spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
304 ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
305
306 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
307 gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
308 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
309 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
310}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 14d6c8249b76..6edc940e0865 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -100,7 +100,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
100 .num_modes = ARRAY_SIZE(fb_modedb), 100 .num_modes = ARRAY_SIZE(fb_modedb),
101}; 101};
102 102
103static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { 103static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
104 /* LCD */ 104 /* LCD */
105 MX35_PAD_LD0__IPU_DISPB_DAT_0, 105 MX35_PAD_LD0__IPU_DISPB_DAT_0,
106 MX35_PAD_LD1__IPU_DISPB_DAT_1, 106 MX35_PAD_LD1__IPU_DISPB_DAT_1,
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 66b2b564c463..76af2c03c241 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -112,7 +112,6 @@
112#include "mx21.h" 112#include "mx21.h"
113#include "mx27.h" 113#include "mx27.h"
114#include "mx1.h" 114#include "mx1.h"
115#include "mx25.h"
116 115
117#define imx_map_entry(soc, name, _type) { \ 116#define imx_map_entry(soc, name, _type) { \
118 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 117 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/mach-imx/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h
deleted file mode 100644
index be51e838375c..000000000000
--- a/arch/arm/mach-imx/iomux-mx25.h
+++ /dev/null
@@ -1,524 +0,0 @@
1/*
2 * arch/arm/plat-mxc/include/mach/iomux-mx25.h
3 *
4 * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
5 *
6 * based on arch/arm/mach-mx25/mx25_pins.h
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * and
9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h
10 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19#ifndef __MACH_IOMUX_MX25_H__
20#define __MACH_IOMUX_MX25_H__
21
22#include "iomux-v3.h"
23
24/*
25 * IOMUX/PAD Bit field definitions
26 */
27
28#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
29#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
30
31#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
32#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
33
34#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
35#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
36
37#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
38#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
39
40#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
41#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
42
43#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
44#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
45
46#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
47#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
48#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
49
50#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
51#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
52#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
53
54#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
55#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
56#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
57
58#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
59#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
60#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
61
62#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
63#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
64
65#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
66#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
67
68#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
69#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
70#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
71
72#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
73#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
74#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
75
76#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
77#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
78#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
79
80#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
81#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
82#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
83
84#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
85#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
86#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
87
88#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
89#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
90
91#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
92#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
93#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
94
95#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
96#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
97#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
98#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
99
100#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
101#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
102#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
103#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
104
105#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
106#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
107
108#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
109#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
110#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
111
112#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
113#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
114#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
115
116#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
117#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
118
119#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
120#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
121#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
122
123#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
124#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
125
126#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
127#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
128
129#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
130#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
131
132#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
133#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
134
135#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
136#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
137
138#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
139#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
140
141#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
142#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
143#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
144
145#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
146#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
147#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
148
149#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
150#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
151#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
152
153#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
154#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
155
156#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
157#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
158
159#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
160#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
161#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
162
163#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
164#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
165#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
166
167#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
168#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
169#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
170
171#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
172#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
173
174#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
175#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
176
177#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
178#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
179
180#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
181#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
182
183#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
184#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
185
186#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
187#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
188
189#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
190#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
191
192#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
193#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
194
195#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
196#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
197#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
198
199#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
200#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
201#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
202
203#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
204#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
205
206#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
207#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
208
209#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
210#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
211
212#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
213#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
214
215#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
216#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
217
218#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
219#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
220
221#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
222#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
223
224#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
225#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
226
227#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
228#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
229
230#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
231#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
232
233#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
234#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
235
236#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
237#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
238
239#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
240#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
241
242#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
243#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
244
245#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
246#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
247
248#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
249#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
250
251#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
252#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
253
254#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
255#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
256
257#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
258#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
259#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
260
261#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
262#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
263#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
264
265#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
266#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
267#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
268#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
269
270#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
271#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
272#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
273
274#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
275#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
276#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
277#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
278
279#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
280#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
281#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
282
283#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
284#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
285
286#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
287#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
288
289#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
290#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
291
292#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
293#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
294
295#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
296#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
297
298#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
299#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
300
301#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
302#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
303
304#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
305#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
306
307#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
308#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
309
310#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
311#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
312
313#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
314#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
315
316#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
317#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
318
319#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
320#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
321
322#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
323#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
324
325#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
326#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
327
328#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
329#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
330
331#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
332#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
333
334#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
335#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
336
337#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
338#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
339#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
340
341#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
342#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
343#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
344
345#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
346#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
347
348#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
349#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
350
351#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
352#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
353#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
354
355#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
356#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
357#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
358
359#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
360#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
361#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
362
363#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
364#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
365#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
366
367#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
368#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
369
370#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
371#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
372#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
373
374#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
375#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
376#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
377
378#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
379#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
380#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
381
382#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
383#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
384
385#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
386#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
387
388#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
389#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
390
391#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
392#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
393#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
394
395#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
396#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
397#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
398
399#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
400#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
401#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
402#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
403
404#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
405#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
406#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
407#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
408
409#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
410#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
411#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
412#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
413
414#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
415#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
416#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
417#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
418
419#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
420#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
421#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
422
423#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
424#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
425#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
426
427#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
428#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
429
430#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
431#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
432#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
433
434#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
435#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
436
437#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
438#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
439
440#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
441#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
442
443#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
444#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
445#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
446
447#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
448#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
449
450#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
451#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
452#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
453
454#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
455#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
456
457#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
458
459#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
460#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
461#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
462
463#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
464#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
465#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
466
467#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
468#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
469
470#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
471#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
472#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
473
474#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
475#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
476#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
477
478#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
479#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
480
481#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
482#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
483
484#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
485#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
486
487#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
488#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
489#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
490#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
491#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
492
493#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
494#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
495#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
496
497#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
498#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
499
500#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
501#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
502#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
503#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
504
505#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
506#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
507#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
508#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
509#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
510#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
511#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
512#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
513#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
514#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
515#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
516#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
517#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
518#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
519#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
520#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
521#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
522#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
523
524#endif /* __MACH_IOMUX_MX25_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 0a5adba61e0b..2e4a0ddca76c 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -114,7 +114,7 @@ enum iomux_gp_func {
114 */ 114 */
115int mxc_iomux_alloc_pin(unsigned int pin, const char *label); 115int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
116/* 116/*
117 * setups mutliple pins 117 * setups multiple pins
118 * convenient way to call the above function with tables 118 * convenient way to call the above function with tables
119 */ 119 */
120int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, 120int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index d61f9606fc56..a53b2e64f98d 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
56 return 0; 56 return 0;
57} 57}
58 58
59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
60 unsigned count)
60{ 61{
61 iomux_v3_cfg_t *p = pad_list; 62 const iomux_v3_cfg_t *p = pad_list;
62 int i; 63 int i;
63 int ret; 64 int ret;
64 65
diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
index 2fa3b5430102..f79e165a3b3c 100644
--- a/arch/arm/mach-imx/iomux-v3.h
+++ b/arch/arm/mach-imx/iomux-v3.h
@@ -128,10 +128,11 @@ typedef u64 iomux_v3_cfg_t;
128int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); 128int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
129 129
130/* 130/*
131 * setups mutliple pads 131 * setups multiple pads
132 * convenient way to call the above function with tables 132 * convenient way to call the above function with tables
133 */ 133 */
134int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); 134int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
135 unsigned count);
135 136
136/* 137/*
137 * Initialise the iomux controller 138 * Initialise the iomux controller
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 62a6e02f4763..922ffd6ca039 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
75 }, 75 },
76}; 76};
77 77
78static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { 78static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
79 /* UART1 */ 79 /* UART1 */
80 MX35_PAD_CTS1__UART1_CTS, 80 MX35_PAD_CTS1__UART1_CTS,
81 MX35_PAD_RTS1__UART1_RTS, 81 MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
deleted file mode 100644
index b2ee6e009fe4..000000000000
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
3 * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/gpio.h>
26#include <linux/platform_device.h>
27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/memory.h>
34#include <asm/mach/map.h>
35
36#include "common.h"
37#include "devices-imx25.h"
38#include "ehci.h"
39#include "eukrea-baseboards.h"
40#include "hardware.h"
41#include "iomux-mx25.h"
42#include "mx25.h"
43
44static const struct imxuart_platform_data uart_pdata __initconst = {
45 .flags = IMXUART_HAVE_RTSCTS,
46};
47
48static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
49 /* FEC - RMII */
50 MX25_PAD_FEC_MDC__FEC_MDC,
51 MX25_PAD_FEC_MDIO__FEC_MDIO,
52 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
53 MX25_PAD_FEC_TDATA1__FEC_TDATA1,
54 MX25_PAD_FEC_TX_EN__FEC_TX_EN,
55 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
56 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
57 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
58 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
59 /* I2C1 */
60 MX25_PAD_I2C1_CLK__I2C1_CLK,
61 MX25_PAD_I2C1_DAT__I2C1_DAT,
62};
63
64static const struct fec_platform_data mx25_fec_pdata __initconst = {
65 .phy = PHY_INTERFACE_MODE_RMII,
66};
67
68static const struct mxc_nand_platform_data
69eukrea_cpuimx25_nand_board_info __initconst = {
70 .width = 1,
71 .hw_ecc = 1,
72 .flash_bbt = 1,
73};
74
75static const struct imxi2c_platform_data
76eukrea_cpuimx25_i2c0_data __initconst = {
77 .bitrate = 100000,
78};
79
80static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
81 {
82 I2C_BOARD_INFO("pcf8563", 0x51),
83 },
84};
85
86static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
87{
88 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
89}
90
91static const struct mxc_usbh_platform_data otg_pdata __initconst = {
92 .init = eukrea_cpuimx25_otg_init,
93 .portsc = MXC_EHCI_MODE_UTMI,
94};
95
96static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
97{
98 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
99 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
100}
101
102static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
103 .init = eukrea_cpuimx25_usbh2_init,
104 .portsc = MXC_EHCI_MODE_SERIAL,
105};
106
107static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
108 .operating_mode = FSL_USB2_DR_DEVICE,
109 .phy_mode = FSL_USB2_PHY_UTMI,
110 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
111};
112
113static bool otg_mode_host __initdata;
114
115static int __init eukrea_cpuimx25_otg_mode(char *options)
116{
117 if (!strcmp(options, "host"))
118 otg_mode_host = true;
119 else if (!strcmp(options, "device"))
120 otg_mode_host = false;
121 else
122 pr_info("otg_mode neither \"host\" nor \"device\". "
123 "Defaulting to device\n");
124 return 1;
125}
126__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
127
128static void __init eukrea_cpuimx25_init(void)
129{
130 imx25_soc_init();
131
132 if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
133 ARRAY_SIZE(eukrea_cpuimx25_pads)))
134 printk(KERN_ERR "error setting cpuimx25 pads !\n");
135
136 imx25_add_imx_uart0(&uart_pdata);
137 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
138 imx25_add_imxdi_rtc();
139 imx25_add_fec(&mx25_fec_pdata);
140 imx25_add_imx2_wdt();
141
142 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
143 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
144 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
145
146 if (otg_mode_host)
147 imx25_add_mxc_ehci_otg(&otg_pdata);
148 else
149 imx25_add_fsl_usb2_udc(&otg_device_pdata);
150
151 imx25_add_mxc_ehci_hs(&usbh2_pdata);
152
153#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
154 eukrea_mbimxsd25_baseboard_init();
155#endif
156}
157
158static void __init eukrea_cpuimx25_timer_init(void)
159{
160 mx25_clocks_init();
161}
162
163MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
164 /* Maintainer: Eukrea Electromatique */
165 .atag_offset = 0x100,
166 .map_io = mx25_map_io,
167 .init_early = imx25_init_early,
168 .init_irq = mx25_init_irq,
169 .init_time = eukrea_cpuimx25_timer_init,
170 .init_machine = eukrea_cpuimx25_init,
171 .restart = mxc_restart,
172MACHINE_END
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/mach-imx25.c
index 25defbdb06c4..9379fd0a7b4d 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/mach-imx25.c
@@ -10,12 +10,29 @@
10 */ 10 */
11 11
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/of_address.h>
13#include <linux/of_irq.h> 14#include <linux/of_irq.h>
14#include <linux/of_platform.h> 15#include <linux/of_platform.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/time.h> 17#include <asm/mach/time.h>
17#include "common.h" 18#include "common.h"
18#include "mx25.h" 19#include "hardware.h"
20
21static void __init imx25_init_early(void)
22{
23 mxc_set_cpu_type(MXC_CPU_MX25);
24}
25
26static void __init mx25_init_irq(void)
27{
28 struct device_node *np;
29 void __iomem *avic_base;
30
31 np = of_find_compatible_node(NULL, NULL, "fsl,avic");
32 avic_base = of_iomap(np, 0);
33 BUG_ON(!avic_base);
34 mxc_init_irq(avic_base);
35}
19 36
20static const char * const imx25_dt_board_compat[] __initconst = { 37static const char * const imx25_dt_board_compat[] __initconst = {
21 "fsl,imx25", 38 "fsl,imx25",
@@ -23,7 +40,6 @@ static const char * const imx25_dt_board_compat[] __initconst = {
23}; 40};
24 41
25DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") 42DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
26 .map_io = mx25_map_io,
27 .init_early = imx25_init_early, 43 .init_early = imx25_init_early,
28 .init_irq = mx25_init_irq, 44 .init_irq = mx25_init_irq,
29 .dt_compat = imx25_dt_board_compat, 45 .dt_compat = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
deleted file mode 100644
index 0d01e367b062..000000000000
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/*
2 * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
16 * Boston, MA 02110-1301, USA.
17 */
18
19/*
20 * This machine is known as:
21 * - i.MX25 3-Stack Development System
22 * - i.MX25 Platform Development Kit (i.MX25 PDK)
23 */
24
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/gpio.h>
31#include <linux/platform_device.h>
32#include <linux/usb/otg.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
39
40#include "common.h"
41#include "devices-imx25.h"
42#include "ehci.h"
43#include "hardware.h"
44#include "iomux-mx25.h"
45#include "mx25.h"
46
47#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6)
48
49static const struct imxuart_platform_data uart_pdata __initconst = {
50 .flags = IMXUART_HAVE_RTSCTS,
51};
52
53static iomux_v3_cfg_t mx25pdk_pads[] = {
54 MX25_PAD_FEC_MDC__FEC_MDC,
55 MX25_PAD_FEC_MDIO__FEC_MDIO,
56 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
57 MX25_PAD_FEC_TDATA1__FEC_TDATA1,
58 MX25_PAD_FEC_TX_EN__FEC_TX_EN,
59 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
60 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
61 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
62 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
63 MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
64 MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
65
66 /* LCD */
67 MX25_PAD_LD0__LD0,
68 MX25_PAD_LD1__LD1,
69 MX25_PAD_LD2__LD2,
70 MX25_PAD_LD3__LD3,
71 MX25_PAD_LD4__LD4,
72 MX25_PAD_LD5__LD5,
73 MX25_PAD_LD6__LD6,
74 MX25_PAD_LD7__LD7,
75 MX25_PAD_LD8__LD8,
76 MX25_PAD_LD9__LD9,
77 MX25_PAD_LD10__LD10,
78 MX25_PAD_LD11__LD11,
79 MX25_PAD_LD12__LD12,
80 MX25_PAD_LD13__LD13,
81 MX25_PAD_LD14__LD14,
82 MX25_PAD_LD15__LD15,
83 MX25_PAD_GPIO_E__LD16,
84 MX25_PAD_GPIO_F__LD17,
85 MX25_PAD_HSYNC__HSYNC,
86 MX25_PAD_VSYNC__VSYNC,
87 MX25_PAD_LSCLK__LSCLK,
88 MX25_PAD_OE_ACD__OE_ACD,
89 MX25_PAD_CONTRAST__CONTRAST,
90
91 /* Keypad */
92 MX25_PAD_KPP_ROW0__KPP_ROW0,
93 MX25_PAD_KPP_ROW1__KPP_ROW1,
94 MX25_PAD_KPP_ROW2__KPP_ROW2,
95 MX25_PAD_KPP_ROW3__KPP_ROW3,
96 MX25_PAD_KPP_COL0__KPP_COL0,
97 MX25_PAD_KPP_COL1__KPP_COL1,
98 MX25_PAD_KPP_COL2__KPP_COL2,
99 MX25_PAD_KPP_COL3__KPP_COL3,
100
101 /* SD1 */
102 MX25_PAD_SD1_CMD__SD1_CMD,
103 MX25_PAD_SD1_CLK__SD1_CLK,
104 MX25_PAD_SD1_DATA0__SD1_DATA0,
105 MX25_PAD_SD1_DATA1__SD1_DATA1,
106 MX25_PAD_SD1_DATA2__SD1_DATA2,
107 MX25_PAD_SD1_DATA3__SD1_DATA3,
108 MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
109 MX25_PAD_A15__GPIO_2_1, /* CardDetect */
110
111 /* I2C1 */
112 MX25_PAD_I2C1_CLK__I2C1_CLK,
113 MX25_PAD_I2C1_DAT__I2C1_DAT,
114
115 /* CAN1 */
116 MX25_PAD_GPIO_A__CAN1_TX,
117 MX25_PAD_GPIO_B__CAN1_RX,
118 MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
119};
120
121static const struct fec_platform_data mx25_fec_pdata __initconst = {
122 .phy = PHY_INTERFACE_MODE_RMII,
123};
124
125#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3)
126#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8)
127
128static void __init mx25pdk_fec_reset(void)
129{
130 gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
131 gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
132
133 gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
134 gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
135 udelay(2);
136
137 /* turn on PHY power and lift reset */
138 gpio_set_value(FEC_ENABLE_GPIO, 1);
139 gpio_set_value(FEC_RESET_B_GPIO, 1);
140}
141
142static const struct mxc_nand_platform_data
143mx25pdk_nand_board_info __initconst = {
144 .width = 1,
145 .hw_ecc = 1,
146 .flash_bbt = 1,
147};
148
149static struct imx_fb_videomode mx25pdk_modes[] = {
150 {
151 .mode = {
152 .name = "CRT-VGA",
153 .refresh = 60,
154 .xres = 640,
155 .yres = 480,
156 .pixclock = 39683,
157 .left_margin = 45,
158 .right_margin = 114,
159 .upper_margin = 33,
160 .lower_margin = 11,
161 .hsync_len = 1,
162 .vsync_len = 1,
163 },
164 .bpp = 16,
165 .pcr = 0xFA208B80,
166 },
167};
168
169static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
170 .mode = mx25pdk_modes,
171 .num_modes = ARRAY_SIZE(mx25pdk_modes),
172 .pwmr = 0x00A903FF,
173 .lscr1 = 0x00120300,
174 .dmacr = 0x00020010,
175};
176
177static const uint32_t mx25pdk_keymap[] = {
178 KEY(0, 0, KEY_UP),
179 KEY(0, 1, KEY_DOWN),
180 KEY(0, 2, KEY_VOLUMEDOWN),
181 KEY(0, 3, KEY_HOME),
182 KEY(1, 0, KEY_RIGHT),
183 KEY(1, 1, KEY_LEFT),
184 KEY(1, 2, KEY_ENTER),
185 KEY(1, 3, KEY_VOLUMEUP),
186 KEY(2, 0, KEY_F6),
187 KEY(2, 1, KEY_F8),
188 KEY(2, 2, KEY_F9),
189 KEY(2, 3, KEY_F10),
190 KEY(3, 0, KEY_F1),
191 KEY(3, 1, KEY_F2),
192 KEY(3, 2, KEY_F3),
193 KEY(3, 3, KEY_POWER),
194};
195
196static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
197 .keymap = mx25pdk_keymap,
198 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
199};
200
201static int mx25pdk_usbh2_init(struct platform_device *pdev)
202{
203 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
204}
205
206static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
207 .init = mx25pdk_usbh2_init,
208 .portsc = MXC_EHCI_MODE_SERIAL,
209};
210
211static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
212 .operating_mode = FSL_USB2_DR_DEVICE,
213 .phy_mode = FSL_USB2_PHY_UTMI,
214};
215
216static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
217 .bitrate = 100000,
218};
219
220#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
221#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
222
223static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
224 .wp_gpio = SD1_GPIO_WP,
225 .cd_gpio = SD1_GPIO_CD,
226 .wp_type = ESDHC_WP_GPIO,
227 .cd_type = ESDHC_CD_GPIO,
228};
229
230static void __init mx25pdk_init(void)
231{
232 imx25_soc_init();
233
234 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
235 ARRAY_SIZE(mx25pdk_pads));
236
237 imx25_add_imx_uart0(&uart_pdata);
238 imx25_add_fsl_usb2_udc(&otg_device_pdata);
239 imx25_add_mxc_ehci_hs(&usbh2_pdata);
240 imx25_add_mxc_nand(&mx25pdk_nand_board_info);
241 imx25_add_imxdi_rtc();
242 imx25_add_imx_fb(&mx25pdk_fb_pdata);
243 imx25_add_imx2_wdt();
244
245 mx25pdk_fec_reset();
246 imx25_add_fec(&mx25_fec_pdata);
247 imx25_add_imx_keypad(&mx25pdk_keymap_data);
248
249 imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
250 imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
251
252 gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
253 imx25_add_flexcan0();
254}
255
256static void __init mx25pdk_timer_init(void)
257{
258 mx25_clocks_init();
259}
260
261MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
262 /* Maintainer: Freescale Semiconductor, Inc. */
263 .atag_offset = 0x100,
264 .map_io = mx25_map_io,
265 .init_early = imx25_init_early,
266 .init_irq = mx25_init_irq,
267 .init_time = mx25pdk_timer_init,
268 .init_machine = mx25pdk_init,
269 .restart = mxc_restart,
270MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 72cd77d21f63..7e315f00648d 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -166,7 +166,7 @@ static struct platform_device *devices[] __initdata = {
166 &mx35pdk_flash, 166 &mx35pdk_flash,
167}; 167};
168 168
169static iomux_v3_cfg_t mx35pdk_pads[] = { 169static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
170 /* UART1 */ 170 /* UART1 */
171 MX35_PAD_CTS1__UART1_CTS, 171 MX35_PAD_CTS1__UART1_CTS,
172 MX35_PAD_RTS1__UART1_RTS, 172 MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index b623bcaca76c..e447e59c0604 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
129 &pcm043_flash, 129 &pcm043_flash,
130}; 130};
131 131
132static iomux_v3_cfg_t pcm043_pads[] = { 132static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
133 /* UART1 */ 133 /* UART1 */
134 MX35_PAD_CTS1__UART1_CTS, 134 MX35_PAD_CTS1__UART1_CTS,
135 MX35_PAD_RTS1__UART1_RTS, 135 MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 97836e94451c..27a8f7e3ec08 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
161 } 161 }
162}; 162};
163 163
164static iomux_v3_cfg_t vpr200_pads[] = { 164static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
165 /* UART1 */ 165 /* UART1 */
166 MX35_PAD_TXD1__UART1_TXD_MUX, 166 MX35_PAD_TXD1__UART1_TXD_MUX,
167 MX35_PAD_RXD1__UART1_RXD_MUX, 167 MX35_PAD_RXD1__UART1_RXD_MUX,
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
deleted file mode 100644
index 5211f62c624e..000000000000
--- a/arch/arm/mach-imx/mm-imx25.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22#include <linux/pinctrl/machine.h>
23
24#include <asm/pgtable.h>
25#include <asm/mach/map.h>
26
27#include "common.h"
28#include "devices/devices-common.h"
29#include "hardware.h"
30#include "iomux-v3.h"
31#include "mx25.h"
32
33/*
34 * This table defines static virtual address mappings for I/O regions.
35 * These are the mappings common across all MX25 boards.
36 */
37static struct map_desc mx25_io_desc[] __initdata = {
38 imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
39 imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
40 imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
41};
42
43/*
44 * This function initializes the memory map. It is called during the
45 * system startup to create static physical to virtual memory mappings
46 * for the IO modules.
47 */
48void __init mx25_map_io(void)
49{
50 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
51}
52
53void __init imx25_init_early(void)
54{
55 mxc_set_cpu_type(MXC_CPU_MX25);
56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
57}
58
59void __init mx25_init_irq(void)
60{
61 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
62}
63
64static struct sdma_platform_data imx25_sdma_pdata __initdata = {
65 .fw_name = "sdma-imx25.bin",
66};
67
68static const struct resource imx25_audmux_res[] __initconst = {
69 DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
70};
71
72void __init imx25_soc_init(void)
73{
74 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
75 mxc_device_init();
76
77 /* i.mx25 has the i.mx35 type gpio */
78 mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
79 mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
80 mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
81 mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
82
83 pinctrl_provide_dummies();
84 /* i.mx25 has the i.mx35 type sdma */
85 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
86 /* i.mx25 has the i.mx31 type audmux */
87 platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
88 ARRAY_SIZE(imx25_audmux_res));
89}
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h
deleted file mode 100644
index ec466400a200..000000000000
--- a/arch/arm/mach-imx/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_SIZE SZ_1M
6#define MX25_AIPS2_BASE_ADDR 0x53f00000
7#define MX25_AIPS2_SIZE SZ_1M
8#define MX25_AVIC_BASE_ADDR 0x68000000
9#define MX25_AVIC_SIZE SZ_1M
10
11#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
12#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
13#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
14#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
15#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
16#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
17#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
18
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
30
31#define MX25_UART1_BASE_ADDR 0x43f90000
32#define MX25_UART2_BASE_ADDR 0x43f94000
33#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
34#define MX25_UART3_BASE_ADDR 0x5000c000
35#define MX25_UART4_BASE_ADDR 0x50008000
36#define MX25_UART5_BASE_ADDR 0x5002c000
37
38#define MX25_CSPI3_BASE_ADDR 0x50004000
39#define MX25_CSPI2_BASE_ADDR 0x50010000
40#define MX25_FEC_BASE_ADDR 0x50038000
41#define MX25_SSI2_BASE_ADDR 0x50014000
42#define MX25_SSI1_BASE_ADDR 0x50034000
43#define MX25_NFC_BASE_ADDR 0xbb000000
44#define MX25_IIM_BASE_ADDR 0x53ff0000
45#define MX25_DRYICE_BASE_ADDR 0x53ffc000
46#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
47#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
48#define MX25_LCDC_BASE_ADDR 0x53fbc000
49#define MX25_KPP_BASE_ADDR 0x43fa8000
50#define MX25_SDMA_BASE_ADDR 0x53fd4000
51#define MX25_USB_BASE_ADDR 0x53ff4000
52#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
53/*
54 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
55 * for the host controller. Early documentation drafts specified 0x400 and
56 * Freescale internal sources confirm only the latter value to work.
57 */
58#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
59#define MX25_CSI_BASE_ADDR 0x53ff8000
60
61#define MX25_IO_P2V(x) IMX_IO_P2V(x)
62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63
64/*
65 * Interrupt numbers
66 */
67#include <asm/irq.h>
68#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
69#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
70#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
71#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
72#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
73#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
74#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
75#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
76#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
77#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
78#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
79#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
80#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
81#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
82#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
83#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
84#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
85#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
86#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
87#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
88#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
89#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
90#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
91#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
92#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
93#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
94#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
95#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
96#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
97#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
101#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
102#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
103
104#define MX25_DMA_REQ_SSI2_RX1 22
105#define MX25_DMA_REQ_SSI2_TX1 23
106#define MX25_DMA_REQ_SSI2_RX0 24
107#define MX25_DMA_REQ_SSI2_TX0 25
108#define MX25_DMA_REQ_SSI1_RX1 26
109#define MX25_DMA_REQ_SSI1_TX1 27
110#define MX25_DMA_REQ_SSI1_RX0 28
111#define MX25_DMA_REQ_SSI1_TX0 29
112
113#ifndef __ASSEMBLY__
114extern int mx25_revision(void);
115#endif
116
117#endif /* ifndef __MACH_MX25_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 12:32:18 -0500