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authorPavel Pisa <ppisa@pikron.com>2007-01-12 03:57:22 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-01-24 06:59:56 -0500
commit5225cd8079484ed27cd52040e8584616d1ef1e2c (patch)
treeb0e13402a8845e996ec4b4b7e043786cbe78d3cf /arch/arm/mach-imx
parent3ea163e44c041b9e1d7314998dfbfd4fbc6eea20 (diff)
[ARM] 4092/1: i.MX/MX1 CPU Frequency scaling latency definition
The transition latency has to be defined and reasonably small to allow on-demand and conservative governors. The value has been defined according to manual. The imx_set_target() protected against seen out of range requests now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/cpufreq.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index ac5f99895660..4f66e90db74f 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -184,6 +184,17 @@ static int imx_set_target(struct cpufreq_policy *policy,
184 long sysclk; 184 long sysclk;
185 unsigned int bclk_div = 1; 185 unsigned int bclk_div = 1;
186 186
187 /*
188 * Some governors do not respects CPU and policy lower limits
189 * which leads to bad things (division by zero etc), ensure
190 * that such things do not happen.
191 */
192 if(target_freq < policy->cpuinfo.min_freq)
193 target_freq = policy->cpuinfo.min_freq;
194
195 if(target_freq < policy->min)
196 target_freq = policy->min;
197
187 freq = target_freq * 1000; 198 freq = target_freq * 1000;
188 199
189 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", 200 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
@@ -258,7 +269,8 @@ static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
258 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 269 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
259 policy->cpuinfo.min_freq = 8000; 270 policy->cpuinfo.min_freq = 8000;
260 policy->cpuinfo.max_freq = 200000; 271 policy->cpuinfo.max_freq = 200000;
261 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 272 /* Manual states, that PLL stabilizes in two CLK32 periods */
273 policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32;
262 return 0; 274 return 0;
263} 275}
264 276