ARM: imx: Get the silicon version from the IIM module

Instead of reading the silicon version from ROM, we should
read the SREV register from the IIM.

Freescale has dropped all support for MX51 REV1.0, only MX51
REV 2.0 and 3.0 are valid.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 24 insertions, 12 deletions

diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 98a25bada783..2202b88667b5 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
         if (clk->parent == parent)
                 return 0;
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 if (parent == &mpll_main1_clk) {
                         cscr |= CCM_CSCR_ARM_SRC;
                 } else {
@@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
         div--;
 
         reg = __raw_readl(CCM_CSCR);
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 reg &= ~(3 << 12);
                 reg |= div << 12;
                 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 pdf += 4;  /* MX27 TO2+ */
         else
                 pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
@@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
         else
                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
                 vpu_pdf += 4;
         } else {
@@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
          * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
          * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
          */
-        if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
                 return 2UL * parent_rate / 3UL;
 
         return parent_rate;
@@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
         /* On TO2 we have to write the value back. Otherwise we
          * read 0 from this register the next time.
          */
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 __raw_writel(reg, CCM_SPCTL0);
 
         return mxc_decode_pll(reg, rate);
@@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
         u32 div;
         unsigned long rate;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
         else
                 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
 {
         unsigned long rate, bclk_pdf;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
         else
                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
 {
         unsigned long rate, ipg_pdf;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 return clk_get_rate(clk->parent);
         else
                 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
 {
         unsigned long cscr = __raw_readl(CCM_CSCR);
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 if (cscr & CCM_CSCR_ARM_SRC)
                         cpu_clk.parent = &mpll_main1_clk;
 
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..3b117be37bd2 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
         val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
                                 + SYS_CHIP_ID));
 
-        cpu_silicon_rev = (int)(val >> 28);
+        switch (val >> 28) {
+        case 0:
+                cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+                break;
+        case 1:
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+                break;
+        case 2:
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+                break;
+        default:
+                cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
+        }
         cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }