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authorShawn Guo <shawn.guo@linaro.org>2012-12-04 09:55:13 -0500
committerShawn Guo <shawn.guo@linaro.org>2013-01-30 08:08:34 -0500
commit485863b8fa02d515e48ce6b59f01d62172d2fe0d (patch)
treea5c6d41091969282e7b34208b191138a76326a7c /arch/arm/mach-imx
parenteea8e326ff476e418b99b6daa97f9bd85ac6c523 (diff)
ARM: imx: mask gpc interrupts initially
Mask gpc interrupts initially to avoid suspicious interrupts. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/gpc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index e1537f9e45b8..722e5df7e44e 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d)
101void __init imx_gpc_init(void) 101void __init imx_gpc_init(void)
102{ 102{
103 struct device_node *np; 103 struct device_node *np;
104 int i;
104 105
105 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 106 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
106 gpc_base = of_iomap(np, 0); 107 gpc_base = of_iomap(np, 0);
107 WARN_ON(!gpc_base); 108 WARN_ON(!gpc_base);
108 109
110 /* Initially mask all interrupts */
111 for (i = 0; i < IMR_NUM; i++)
112 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
113
109 /* Register GPC as the secondary interrupt controller behind GIC */ 114 /* Register GPC as the secondary interrupt controller behind GIC */
110 gic_arch_extn.irq_mask = imx_gpc_irq_mask; 115 gic_arch_extn.irq_mask = imx_gpc_irq_mask;
111 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; 116 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;