diff options
author | Pavel Pisa <ppisa@pikron.com> | 2006-12-06 11:19:44 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-12-07 11:24:16 -0500 |
commit | 86987d5bf4db7850a8dfb073c6a3506d4e0d2bcc (patch) | |
tree | a3ed39fc3e46ee6f2273cbad8f6d60c0a53e1481 /arch/arm/mach-imx/time.c | |
parent | 5c894cd1c89fc10907febd93e6ef35cd3c65e25e (diff) |
[ARM] 3991/1: i.MX/MX1 high resolution time source
Enhanced resolution for time measurement functions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-imx/time.c')
-rw-r--r-- | arch/arm/mach-imx/time.c | 86 |
1 files changed, 50 insertions, 36 deletions
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 8ae4a2c5066f..40039b2a90b3 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <linux/time.h> | 16 | #include <linux/time.h> |
17 | #include <linux/clocksource.h> | ||
17 | 18 | ||
18 | #include <asm/hardware.h> | 19 | #include <asm/hardware.h> |
19 | #include <asm/io.h> | 20 | #include <asm/io.h> |
@@ -24,33 +25,7 @@ | |||
24 | /* Use timer 1 as system timer */ | 25 | /* Use timer 1 as system timer */ |
25 | #define TIMER_BASE IMX_TIM1_BASE | 26 | #define TIMER_BASE IMX_TIM1_BASE |
26 | 27 | ||
27 | /* | 28 | static unsigned long evt_diff; |
28 | * Returns number of us since last clock interrupt. Note that interrupts | ||
29 | * will have been disabled by do_gettimeoffset() | ||
30 | */ | ||
31 | static unsigned long imx_gettimeoffset(void) | ||
32 | { | ||
33 | unsigned long ticks; | ||
34 | |||
35 | /* | ||
36 | * Get the current number of ticks. Note that there is a race | ||
37 | * condition between us reading the timer and checking for | ||
38 | * an interrupt. We get around this by ensuring that the | ||
39 | * counter has not reloaded between our two reads. | ||
40 | */ | ||
41 | ticks = IMX_TCN(TIMER_BASE); | ||
42 | |||
43 | /* | ||
44 | * Interrupt pending? If so, we've reloaded once already. | ||
45 | */ | ||
46 | if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP) | ||
47 | ticks += LATCH; | ||
48 | |||
49 | /* | ||
50 | * Convert the ticks to usecs | ||
51 | */ | ||
52 | return (1000000 / CLK32) * ticks; | ||
53 | } | ||
54 | 29 | ||
55 | /* | 30 | /* |
56 | * IRQ handler for the timer | 31 | * IRQ handler for the timer |
@@ -58,14 +33,23 @@ static unsigned long imx_gettimeoffset(void) | |||
58 | static irqreturn_t | 33 | static irqreturn_t |
59 | imx_timer_interrupt(int irq, void *dev_id) | 34 | imx_timer_interrupt(int irq, void *dev_id) |
60 | { | 35 | { |
61 | write_seqlock(&xtime_lock); | 36 | uint32_t tstat; |
62 | 37 | ||
63 | /* clear the interrupt */ | 38 | /* clear the interrupt */ |
64 | if (IMX_TSTAT(TIMER_BASE)) | 39 | tstat = IMX_TSTAT(TIMER_BASE); |
65 | IMX_TSTAT(TIMER_BASE) = 0; | 40 | IMX_TSTAT(TIMER_BASE) = 0; |
41 | |||
42 | if (tstat & TSTAT_COMP) { | ||
43 | do { | ||
44 | |||
45 | write_seqlock(&xtime_lock); | ||
46 | timer_tick(); | ||
47 | write_sequnlock(&xtime_lock); | ||
48 | IMX_TCMP(TIMER_BASE) += evt_diff; | ||
66 | 49 | ||
67 | timer_tick(); | 50 | } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE) |
68 | write_sequnlock(&xtime_lock); | 51 | - IMX_TCN(TIMER_BASE)) < 0)); |
52 | } | ||
69 | 53 | ||
70 | return IRQ_HANDLED; | 54 | return IRQ_HANDLED; |
71 | } | 55 | } |
@@ -77,9 +61,9 @@ static struct irqaction imx_timer_irq = { | |||
77 | }; | 61 | }; |
78 | 62 | ||
79 | /* | 63 | /* |
80 | * Set up timer interrupt, and return the current time in seconds. | 64 | * Set up timer hardware into expected mode and state. |
81 | */ | 65 | */ |
82 | static void __init imx_timer_init(void) | 66 | static void __init imx_timer_hardware_init(void) |
83 | { | 67 | { |
84 | /* | 68 | /* |
85 | * Initialise to a known state (all timers off, and timing reset) | 69 | * Initialise to a known state (all timers off, and timing reset) |
@@ -87,7 +71,38 @@ static void __init imx_timer_init(void) | |||
87 | IMX_TCTL(TIMER_BASE) = 0; | 71 | IMX_TCTL(TIMER_BASE) = 0; |
88 | IMX_TPRER(TIMER_BASE) = 0; | 72 | IMX_TPRER(TIMER_BASE) = 0; |
89 | IMX_TCMP(TIMER_BASE) = LATCH - 1; | 73 | IMX_TCMP(TIMER_BASE) = LATCH - 1; |
90 | IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN; | 74 | |
75 | IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN; | ||
76 | evt_diff = LATCH; | ||
77 | } | ||
78 | |||
79 | cycle_t imx_get_cycles(void) | ||
80 | { | ||
81 | return IMX_TCN(TIMER_BASE); | ||
82 | } | ||
83 | |||
84 | static struct clocksource clocksource_imx = { | ||
85 | .name = "imx_timer1", | ||
86 | .rating = 200, | ||
87 | .read = imx_get_cycles, | ||
88 | .mask = 0xFFFFFFFF, | ||
89 | .shift = 20, | ||
90 | .is_continuous = 1, | ||
91 | }; | ||
92 | |||
93 | static int __init imx_clocksource_init(void) | ||
94 | { | ||
95 | clocksource_imx.mult = | ||
96 | clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift); | ||
97 | clocksource_register(&clocksource_imx); | ||
98 | |||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | static void __init imx_timer_init(void) | ||
103 | { | ||
104 | imx_timer_hardware_init(); | ||
105 | imx_clocksource_init(); | ||
91 | 106 | ||
92 | /* | 107 | /* |
93 | * Make irqs happen for the system timer | 108 | * Make irqs happen for the system timer |
@@ -97,5 +112,4 @@ static void __init imx_timer_init(void) | |||
97 | 112 | ||
98 | struct sys_timer imx_timer = { | 113 | struct sys_timer imx_timer = { |
99 | .init = imx_timer_init, | 114 | .init = imx_timer_init, |
100 | .offset = imx_gettimeoffset, | ||
101 | }; | 115 | }; |