diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2012-09-14 02:14:45 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2012-10-14 22:05:43 -0400 |
| commit | 50f2de61269bbe2f40bead1969a9594fa8599b93 (patch) | |
| tree | 842f17cd25c5350f602a3fb31960e34bb3855b21 /arch/arm/mach-imx/mx31.h | |
| parent | 6dde5ac5220b3b9c28f82f291b64eca3e5ebe80d (diff) | |
ARM: imx: include hardware.h rather than mach/hardware.h
It moves a bunch of header files included in hardware.h and itself
from mach-imx/include/mach to mach-imx, and updates users to include
hardware.h rather than mach/hardware.h. The files in mach-imx/devices
will need to include "../hardware.h".
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/mx31.h')
| -rw-r--r-- | arch/arm/mach-imx/mx31.h | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h new file mode 100644 index 000000000000..ee9b1f9215df --- /dev/null +++ b/arch/arm/mach-imx/mx31.h | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | #ifndef __MACH_MX31_H__ | ||
| 2 | #define __MACH_MX31_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IRAM | ||
| 6 | */ | ||
| 7 | #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ | ||
| 8 | #define MX31_IRAM_SIZE SZ_16K | ||
| 9 | |||
| 10 | #define MX31_L2CC_BASE_ADDR 0x30000000 | ||
| 11 | #define MX31_L2CC_SIZE SZ_1M | ||
| 12 | |||
| 13 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 | ||
| 14 | #define MX31_AIPS1_SIZE SZ_1M | ||
| 15 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) | ||
| 16 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) | ||
| 17 | #define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) | ||
| 18 | #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) | ||
| 19 | #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) | ||
| 20 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) | ||
| 21 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) | ||
| 22 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) | ||
| 23 | #define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) | ||
| 24 | #define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) | ||
| 25 | #define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) | ||
| 26 | #define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) | ||
| 27 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) | ||
| 28 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) | ||
| 29 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) | ||
| 30 | #define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) | ||
| 31 | #define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) | ||
| 32 | #define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) | ||
| 33 | #define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) | ||
| 34 | #define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) | ||
| 35 | #define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) | ||
| 36 | #define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) | ||
| 37 | #define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) | ||
| 38 | #define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) | ||
| 39 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) | ||
| 40 | |||
| 41 | #define MX31_SPBA0_BASE_ADDR 0x50000000 | ||
| 42 | #define MX31_SPBA0_SIZE SZ_1M | ||
| 43 | #define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) | ||
| 44 | #define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) | ||
| 45 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) | ||
| 46 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) | ||
| 47 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) | ||
| 48 | #define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) | ||
| 49 | #define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) | ||
| 50 | #define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) | ||
| 51 | #define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) | ||
| 52 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) | ||
| 53 | |||
| 54 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 | ||
| 55 | #define MX31_AIPS2_SIZE SZ_1M | ||
| 56 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) | ||
| 57 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) | ||
| 58 | #define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) | ||
| 59 | #define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) | ||
| 60 | #define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) | ||
| 61 | #define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) | ||
| 62 | #define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) | ||
| 63 | #define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) | ||
| 64 | #define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) | ||
| 65 | #define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) | ||
| 66 | #define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) | ||
| 67 | #define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) | ||
| 68 | #define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) | ||
| 69 | #define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) | ||
| 70 | #define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) | ||
| 71 | #define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) | ||
| 72 | #define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) | ||
| 73 | #define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) | ||
| 74 | #define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) | ||
| 75 | #define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) | ||
| 76 | #define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) | ||
| 77 | |||
| 78 | #define MX31_ROMP_BASE_ADDR 0x60000000 | ||
| 79 | #define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) | ||
| 80 | #define MX31_ROMP_SIZE SZ_1M | ||
| 81 | |||
| 82 | #define MX31_AVIC_BASE_ADDR 0x68000000 | ||
| 83 | #define MX31_AVIC_SIZE SZ_1M | ||
| 84 | |||
| 85 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 | ||
| 86 | #define MX31_CSD0_BASE_ADDR 0x80000000 | ||
| 87 | #define MX31_CSD1_BASE_ADDR 0x90000000 | ||
| 88 | |||
| 89 | #define MX31_CS0_BASE_ADDR 0xa0000000 | ||
| 90 | #define MX31_CS1_BASE_ADDR 0xa8000000 | ||
| 91 | #define MX31_CS2_BASE_ADDR 0xb0000000 | ||
| 92 | #define MX31_CS3_BASE_ADDR 0xb2000000 | ||
| 93 | |||
| 94 | #define MX31_CS4_BASE_ADDR 0xb4000000 | ||
| 95 | #define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) | ||
| 96 | #define MX31_CS4_SIZE SZ_32M | ||
| 97 | |||
| 98 | #define MX31_CS5_BASE_ADDR 0xb6000000 | ||
| 99 | #define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) | ||
| 100 | #define MX31_CS5_SIZE SZ_32M | ||
| 101 | |||
| 102 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 | ||
| 103 | #define MX31_X_MEMC_SIZE SZ_64K | ||
| 104 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) | ||
| 105 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) | ||
| 106 | #define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) | ||
| 107 | #define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) | ||
| 108 | #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) | ||
| 109 | #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR | ||
| 110 | |||
| 111 | #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) | ||
| 112 | #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) | ||
| 113 | #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) | ||
| 114 | #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) | ||
| 115 | |||
| 116 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 | ||
| 117 | |||
| 118 | #define MX31_IO_P2V(x) IMX_IO_P2V(x) | ||
| 119 | #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) | ||
| 120 | |||
| 121 | /* | ||
| 122 | * Interrupt numbers | ||
| 123 | */ | ||
| 124 | #include <asm/irq.h> | ||
| 125 | #define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) | ||
| 126 | #define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) | ||
| 127 | #define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) | ||
| 128 | #define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) | ||
| 129 | #define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) | ||
| 130 | #define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) | ||
| 131 | #define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) | ||
| 132 | #define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) | ||
| 133 | #define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) | ||
| 134 | #define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) | ||
| 135 | #define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) | ||
| 136 | #define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) | ||
| 137 | #define MX31_INT_ATA (NR_IRQS_LEGACY + 15) | ||
| 138 | #define MX31_INT_MBX (NR_IRQS_LEGACY + 16) | ||
| 139 | #define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) | ||
| 140 | #define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) | ||
| 141 | #define MX31_INT_IIM (NR_IRQS_LEGACY + 19) | ||
| 142 | #define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) | ||
| 143 | #define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) | ||
| 144 | #define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) | ||
| 145 | #define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) | ||
| 146 | #define MX31_INT_KPP (NR_IRQS_LEGACY + 24) | ||
| 147 | #define MX31_INT_RTC (NR_IRQS_LEGACY + 25) | ||
| 148 | #define MX31_INT_PWM (NR_IRQS_LEGACY + 26) | ||
| 149 | #define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) | ||
| 150 | #define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) | ||
| 151 | #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) | ||
| 152 | #define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) | ||
| 153 | #define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) | ||
| 154 | #define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) | ||
| 155 | #define MX31_INT_NFC (NR_IRQS_LEGACY + 33) | ||
| 156 | #define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) | ||
| 157 | #define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) | ||
| 158 | #define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) | ||
| 159 | #define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) | ||
| 160 | #define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) | ||
| 161 | #define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) | ||
| 162 | #define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) | ||
| 163 | #define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) | ||
| 164 | #define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) | ||
| 165 | #define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) | ||
| 166 | #define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) | ||
| 167 | #define MX31_INT_ECT (NR_IRQS_LEGACY + 48) | ||
| 168 | #define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) | ||
| 169 | #define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) | ||
| 170 | #define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) | ||
| 171 | #define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) | ||
| 172 | #define MX31_INT_CCM (NR_IRQS_LEGACY + 53) | ||
| 173 | #define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) | ||
| 174 | #define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) | ||
| 175 | #define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) | ||
| 176 | #define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) | ||
| 177 | #define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) | ||
| 178 | #define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) | ||
| 179 | #define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) | ||
| 180 | #define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) | ||
| 181 | #define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) | ||
| 182 | |||
| 183 | #define MX31_DMA_REQ_SDHC1 20 | ||
| 184 | #define MX31_DMA_REQ_SDHC2 21 | ||
| 185 | #define MX31_DMA_REQ_SSI2_RX1 22 | ||
| 186 | #define MX31_DMA_REQ_SSI2_TX1 23 | ||
| 187 | #define MX31_DMA_REQ_SSI2_RX0 24 | ||
| 188 | #define MX31_DMA_REQ_SSI2_TX0 25 | ||
| 189 | #define MX31_DMA_REQ_SSI1_RX1 26 | ||
| 190 | #define MX31_DMA_REQ_SSI1_TX1 27 | ||
| 191 | #define MX31_DMA_REQ_SSI1_RX0 28 | ||
| 192 | #define MX31_DMA_REQ_SSI1_TX0 29 | ||
| 193 | |||
| 194 | #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 195 | |||
| 196 | #endif /* ifndef __MACH_MX31_H__ */ | ||