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authorFabio Estevam <fabio.estevam@freescale.com>2011-06-20 09:37:13 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2011-07-07 03:06:57 -0400
commitb2a08e3e46f594ad605c9b5f5fce6b9f36a9a3eb (patch)
tree6c435bdeb944b7587cd9045ea70914831dc00fb6 /arch/arm/mach-imx/mach-mx31_3ds.c
parent98618cfe22a5dbb87c0deb341734436aeecd51bf (diff)
ARM: mach-imx/mx31_3ds: Fix IOMUX for SPI1 signals
Original code was assuming that the CSPI1 pins on the MX31PDK were the primary pin function, which is incorrect. On MX31PDK board these are the pins that provide CSPI1 functionality: DSR_DCE1 (ALT mode 1) --> CSPI1_CLK RI_DCE1 (ALT mode 1) --> CSPI1_RDY DTR_DTE1 -->CSI1_MOSI DSR_DTE1 --> CSPI1_MISO DTR_DCE2 ---> CSPI1_SS2 The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM. This patch fixes the CSPI1 IOMUX and makes the LCD to be functional. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/mach-mx31_3ds.c')
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 9b982449cb52..62983bd07d6a 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -53,11 +53,8 @@ static int mx31_3ds_pins[] = {
53 MX31_PIN_RXD1__RXD1, 53 MX31_PIN_RXD1__RXD1,
54 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 54 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
55 /*SPI0*/ 55 /*SPI0*/
56 MX31_PIN_CSPI1_SCLK__SCLK, 56 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
57 MX31_PIN_CSPI1_MOSI__MOSI, 57 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
58 MX31_PIN_CSPI1_MISO__MISO,
59 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
60 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
61 /* SPI 1 */ 58 /* SPI 1 */
62 MX31_PIN_CSPI2_SCLK__SCLK, 59 MX31_PIN_CSPI2_SCLK__SCLK,
63 MX31_PIN_CSPI2_MOSI__MOSI, 60 MX31_PIN_CSPI2_MOSI__MOSI,
@@ -689,6 +686,9 @@ static void __init mx31_3ds_init(void)
689{ 686{
690 int ret; 687 int ret;
691 688
689 /* Configure SPI1 IOMUX */
690 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
691
692 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), 692 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
693 "mx31_3ds"); 693 "mx31_3ds");
694 694