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authorShawn Guo <shawn.guo@linaro.org>2012-09-14 02:14:45 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-10-14 22:05:43 -0400
commit50f2de61269bbe2f40bead1969a9594fa8599b93 (patch)
tree842f17cd25c5350f602a3fb31960e34bb3855b21 /arch/arm/mach-imx/include
parent6dde5ac5220b3b9c28f82f291b64eca3e5ebe80d (diff)
ARM: imx: include hardware.h rather than mach/hardware.h
It moves a bunch of header files included in hardware.h and itself from mach-imx/include/mach to mach-imx, and updates users to include hardware.h rather than mach/hardware.h. The files in mach-imx/devices will need to include "../hardware.h". Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/include')
-rw-r--r--arch/arm/mach-imx/include/mach/hardware.h134
-rw-r--r--arch/arm/mach-imx/include/mach/mx1.h172
-rw-r--r--arch/arm/mach-imx/include/mach/mx21.h189
-rw-r--r--arch/arm/mach-imx/include/mach/mx25.h117
-rw-r--r--arch/arm/mach-imx/include/mach/mx27.h238
-rw-r--r--arch/arm/mach-imx/include/mach/mx2x.h145
-rw-r--r--arch/arm/mach-imx/include/mach/mx31.h196
-rw-r--r--arch/arm/mach-imx/include/mach/mx35.h190
-rw-r--r--arch/arm/mach-imx/include/mach/mx3x.h195
-rw-r--r--arch/arm/mach-imx/include/mach/mx50.h290
-rw-r--r--arch/arm/mach-imx/include/mach/mx51.h346
-rw-r--r--arch/arm/mach-imx/include/mach/mx53.h342
-rw-r--r--arch/arm/mach-imx/include/mach/mx6q.h35
-rw-r--r--arch/arm/mach-imx/include/mach/mxc.h179
14 files changed, 0 insertions, 2768 deletions
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
deleted file mode 100644
index ebf10654bb42..000000000000
--- a/arch/arm/mach-imx/include/mach/hardware.h
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
21#define __ASM_ARCH_MXC_HARDWARE_H__
22
23#include <asm/sizes.h>
24
25#define addr_in_module(addr, mod) \
26 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
27
28#define IMX_IO_P2V_MODULE(addr, module) \
29 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
30 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
31
32/*
33 * This is rather complicated for humans and ugly to verify, but for a machine
34 * it's OK. Still more as it is usually only applied to constants. The upsides
35 * on using this approach are:
36 *
37 * - same mapping on all i.MX machines
38 * - works for assembler, too
39 * - no need to nurture #defines for virtual addresses
40 *
41 * The downside it, it's hard to verify (but I have a script for that).
42 *
43 * Obviously this needs to be injective for each SoC. In general it maps the
44 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
45 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
46 *
47 * It applies the following mappings for the different SoCs:
48 *
49 * mx1:
50 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
51 * mx21:
52 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
53 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
54 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
55 * mx25:
56 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
57 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
58 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
59 * mx27:
60 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
61 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
62 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
63 * mx31:
64 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
65 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
66 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
67 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
68 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
69 * mx35:
70 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
71 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
75 * mx50:
76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
77 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
78 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
80 * mx51:
81 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
83 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
84 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
85 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
86 * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
87 * mx53:
88 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
89 * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
90 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
91 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
92 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
93 * mx6q:
94 * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
95 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
96 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
97 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
98 */
99#define IMX_IO_P2V(x) ( \
100 (((x) & 0x80000000) >> 7) | \
101 (0xf4000000 + \
102 (((x) & 0x50000000) >> 6) + \
103 (((x) & 0x0b000000) >> 4) + \
104 (((x) & 0x000fffff))))
105
106#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
107
108#include <mach/mxc.h>
109
110#include <mach/mx6q.h>
111#include <mach/mx50.h>
112#include <mach/mx51.h>
113#include <mach/mx53.h>
114#include <mach/mx3x.h>
115#include <mach/mx31.h>
116#include <mach/mx35.h>
117#include <mach/mx2x.h>
118#include <mach/mx21.h>
119#include <mach/mx27.h>
120#include <mach/mx1.h>
121#include <mach/mx25.h>
122
123#define imx_map_entry(soc, name, _type) { \
124 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
125 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
126 .length = soc ## _ ## name ## _SIZE, \
127 .type = _type, \
128}
129
130/* There's a off-by-one betweem the gpio bank number and the gpiochip */
131/* range e.g. GPIO_1_5 is gpio 5 under linux */
132#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
133
134#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx1.h b/arch/arm/mach-imx/include/mach/mx1.h
deleted file mode 100644
index 45bd31cc34d6..000000000000
--- a/arch/arm/mach-imx/include/mach/mx1.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_MX1_H__
13#define __MACH_MX1_H__
14
15/*
16 * Memory map
17 */
18#define MX1_IO_BASE_ADDR 0x00200000
19#define MX1_IO_SIZE SZ_1M
20
21#define MX1_CS0_PHYS 0x10000000
22#define MX1_CS0_SIZE 0x02000000
23
24#define MX1_CS1_PHYS 0x12000000
25#define MX1_CS1_SIZE 0x01000000
26
27#define MX1_CS2_PHYS 0x13000000
28#define MX1_CS2_SIZE 0x01000000
29
30#define MX1_CS3_PHYS 0x14000000
31#define MX1_CS3_SIZE 0x01000000
32
33#define MX1_CS4_PHYS 0x15000000
34#define MX1_CS4_SIZE 0x01000000
35
36#define MX1_CS5_PHYS 0x16000000
37#define MX1_CS5_SIZE 0x01000000
38
39/*
40 * Register BASEs, based on OFFSETs
41 */
42#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
43#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
44#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
45#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
46#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
47#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
48#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
49#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
50#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
51#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
52#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
53#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
54#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
55#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
56#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
57#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
58#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
59#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
60#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
61#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
62#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
63#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
64#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
65#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
66#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
67#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
70#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
71#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
72#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
73#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
74#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
75
76/* macro to get at IO space when running virtually */
77#define MX1_IO_P2V(x) IMX_IO_P2V(x)
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79
80/* fixed interrput numbers */
81#include <asm/irq.h>
82#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
137
138/* DMA */
139#define MX1_DMA_REQ_UART3_T 2
140#define MX1_DMA_REQ_UART3_R 3
141#define MX1_DMA_REQ_SSI2_T 4
142#define MX1_DMA_REQ_SSI2_R 5
143#define MX1_DMA_REQ_CSI_STAT 6
144#define MX1_DMA_REQ_CSI_R 7
145#define MX1_DMA_REQ_MSHC 8
146#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
147#define MX1_DMA_REQ_DSPA_DCT_DIN 10
148#define MX1_DMA_REQ_DSPA_MAC 11
149#define MX1_DMA_REQ_EXT 12
150#define MX1_DMA_REQ_SDHC 13
151#define MX1_DMA_REQ_SPI1_R 14
152#define MX1_DMA_REQ_SPI1_T 15
153#define MX1_DMA_REQ_SSI_T 16
154#define MX1_DMA_REQ_SSI_R 17
155#define MX1_DMA_REQ_ASP_DAC 18
156#define MX1_DMA_REQ_ASP_ADC 19
157#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
158#define MX1_DMA_REQ_SPI2_R 26
159#define MX1_DMA_REQ_SPI2_T 27
160#define MX1_DMA_REQ_UART2_T 28
161#define MX1_DMA_REQ_UART2_R 29
162#define MX1_DMA_REQ_UART1_T 30
163#define MX1_DMA_REQ_UART1_R 31
164
165/*
166 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
167 * to not break drivers/usb/gadget/imx_udc. Should go
168 * away after this driver uses the new name.
169 */
170#define USBD_INT0 MX1_INT_USBD0
171
172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx21.h b/arch/arm/mach-imx/include/mach/mx21.h
deleted file mode 100644
index 468738aa997f..000000000000
--- a/arch/arm/mach-imx/include/mach/mx21.h
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __MACH_MX21_H__
26#define __MACH_MX21_H__
27
28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_SIZE SZ_1M
30#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
31#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
32#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
33#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
34#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
35#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
36#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
37#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
38#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
39#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
40#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
41#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
42#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
43#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
44#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
45#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
46#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
47#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
48#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
49#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
50#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
51#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
52#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
53#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
54#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
55#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
56#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
57#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
58#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
59#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
60#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
61#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
62#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
63#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
64#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
65#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
66#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
67#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
68
69#define MX21_AVIC_BASE_ADDR 0x10040000
70
71#define MX21_SAHB1_BASE_ADDR 0x80000000
72#define MX21_SAHB1_SIZE SZ_1M
73#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
74
75/* Memory regions and CS */
76#define MX21_SDRAM_BASE_ADDR 0xc0000000
77#define MX21_CSD1_BASE_ADDR 0xc4000000
78
79#define MX21_CS0_BASE_ADDR 0xc8000000
80#define MX21_CS1_BASE_ADDR 0xcc000000
81#define MX21_CS2_BASE_ADDR 0xd0000000
82#define MX21_CS3_BASE_ADDR 0xd1000000
83#define MX21_CS4_BASE_ADDR 0xd2000000
84#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
85#define MX21_CS5_BASE_ADDR 0xdd000000
86
87/* NAND, SDRAM, WEIM etc controllers */
88#define MX21_X_MEMC_BASE_ADDR 0xdf000000
89#define MX21_X_MEMC_SIZE SZ_256K
90
91#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
92#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
93#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
94#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
95
96#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
97
98#define MX21_IO_P2V(x) IMX_IO_P2V(x)
99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
100
101/* fixed interrupt numbers */
102#include <asm/irq.h>
103#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
104#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
105#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
106#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
107#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
108#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
109#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
110#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
111#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
112#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
113#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
114#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
115#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
116#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
117#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
118#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
119#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
120#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
121#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
122#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
123#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
124#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
125#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
126#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
127#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
128#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
129#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
130#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
131#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
132#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
133#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
134#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
135#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
136#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
137#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
138#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
139#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
140#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
141#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
142#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
143#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
144#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
145#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
146#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
147#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
148#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
149#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
150#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
151#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
152#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
153#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
154#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
155#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
156
157/* fixed DMA request numbers */
158#define MX21_DMA_REQ_CSPI3_RX 1
159#define MX21_DMA_REQ_CSPI3_TX 2
160#define MX21_DMA_REQ_EXT 3
161#define MX21_DMA_REQ_FIRI_RX 4
162#define MX21_DMA_REQ_SDHC2 6
163#define MX21_DMA_REQ_SDHC1 7
164#define MX21_DMA_REQ_SSI2_RX0 8
165#define MX21_DMA_REQ_SSI2_TX0 9
166#define MX21_DMA_REQ_SSI2_RX1 10
167#define MX21_DMA_REQ_SSI2_TX1 11
168#define MX21_DMA_REQ_SSI1_RX0 12
169#define MX21_DMA_REQ_SSI1_TX0 13
170#define MX21_DMA_REQ_SSI1_RX1 14
171#define MX21_DMA_REQ_SSI1_TX1 15
172#define MX21_DMA_REQ_CSPI2_RX 16
173#define MX21_DMA_REQ_CSPI2_TX 17
174#define MX21_DMA_REQ_CSPI1_RX 18
175#define MX21_DMA_REQ_CSPI1_TX 19
176#define MX21_DMA_REQ_UART4_RX 20
177#define MX21_DMA_REQ_UART4_TX 21
178#define MX21_DMA_REQ_UART3_RX 22
179#define MX21_DMA_REQ_UART3_TX 23
180#define MX21_DMA_REQ_UART2_RX 24
181#define MX21_DMA_REQ_UART2_TX 25
182#define MX21_DMA_REQ_UART1_RX 26
183#define MX21_DMA_REQ_UART1_TX 27
184#define MX21_DMA_REQ_BMI_TX 28
185#define MX21_DMA_REQ_BMI_RX 29
186#define MX21_DMA_REQ_CSI_STAT 30
187#define MX21_DMA_REQ_CSI_RX 31
188
189#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx25.h b/arch/arm/mach-imx/include/mach/mx25.h
deleted file mode 100644
index ec466400a200..000000000000
--- a/arch/arm/mach-imx/include/mach/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_SIZE SZ_1M
6#define MX25_AIPS2_BASE_ADDR 0x53f00000
7#define MX25_AIPS2_SIZE SZ_1M
8#define MX25_AVIC_BASE_ADDR 0x68000000
9#define MX25_AVIC_SIZE SZ_1M
10
11#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
12#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
13#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
14#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
15#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
16#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
17#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
18
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
30
31#define MX25_UART1_BASE_ADDR 0x43f90000
32#define MX25_UART2_BASE_ADDR 0x43f94000
33#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
34#define MX25_UART3_BASE_ADDR 0x5000c000
35#define MX25_UART4_BASE_ADDR 0x50008000
36#define MX25_UART5_BASE_ADDR 0x5002c000
37
38#define MX25_CSPI3_BASE_ADDR 0x50004000
39#define MX25_CSPI2_BASE_ADDR 0x50010000
40#define MX25_FEC_BASE_ADDR 0x50038000
41#define MX25_SSI2_BASE_ADDR 0x50014000
42#define MX25_SSI1_BASE_ADDR 0x50034000
43#define MX25_NFC_BASE_ADDR 0xbb000000
44#define MX25_IIM_BASE_ADDR 0x53ff0000
45#define MX25_DRYICE_BASE_ADDR 0x53ffc000
46#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
47#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
48#define MX25_LCDC_BASE_ADDR 0x53fbc000
49#define MX25_KPP_BASE_ADDR 0x43fa8000
50#define MX25_SDMA_BASE_ADDR 0x53fd4000
51#define MX25_USB_BASE_ADDR 0x53ff4000
52#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
53/*
54 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
55 * for the host controller. Early documentation drafts specified 0x400 and
56 * Freescale internal sources confirm only the latter value to work.
57 */
58#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
59#define MX25_CSI_BASE_ADDR 0x53ff8000
60
61#define MX25_IO_P2V(x) IMX_IO_P2V(x)
62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63
64/*
65 * Interrupt numbers
66 */
67#include <asm/irq.h>
68#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
69#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
70#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
71#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
72#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
73#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
74#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
75#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
76#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
77#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
78#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
79#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
80#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
81#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
82#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
83#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
84#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
85#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
86#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
87#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
88#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
89#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
90#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
91#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
92#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
93#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
94#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
95#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
96#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
97#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
101#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
102#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
103
104#define MX25_DMA_REQ_SSI2_RX1 22
105#define MX25_DMA_REQ_SSI2_TX1 23
106#define MX25_DMA_REQ_SSI2_RX0 24
107#define MX25_DMA_REQ_SSI2_TX0 25
108#define MX25_DMA_REQ_SSI1_RX1 26
109#define MX25_DMA_REQ_SSI1_TX1 27
110#define MX25_DMA_REQ_SSI1_RX0 28
111#define MX25_DMA_REQ_SSI1_TX0 29
112
113#ifndef __ASSEMBLY__
114extern int mx25_revision(void);
115#endif
116
117#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx27.h b/arch/arm/mach-imx/include/mach/mx27.h
deleted file mode 100644
index e074616d54ca..000000000000
--- a/arch/arm/mach-imx/include/mach/mx27.h
+++ /dev/null
@@ -1,238 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
7 * look at mx2x.h.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#ifndef __MACH_MX27_H__
25#define __MACH_MX27_H__
26
27#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_SIZE SZ_1M
29#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
30#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
31#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
32#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
33#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
34#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
35#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
36#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
37#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
38#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
39#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
40#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
41#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
42#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
43#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
44#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
45#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
46#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
47#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
48#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
49#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
50#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
51#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
52#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
53#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
54#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
55#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
56#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
57#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
58#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
59#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
60#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
61#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
62#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
63#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
64#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
65#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
66#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
67#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
68#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
69#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
70#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
71#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
72#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
73#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
74#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
75#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
76#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
77#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
78#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
79#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
80#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
81#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
82#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
83#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
84#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
85#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
86
87#define MX27_AVIC_BASE_ADDR 0x10040000
88
89/* ROM patch */
90#define MX27_ROMP_BASE_ADDR 0x10041000
91
92#define MX27_SAHB1_BASE_ADDR 0x80000000
93#define MX27_SAHB1_SIZE SZ_1M
94#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
95#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
96
97/* Memory regions and CS */
98#define MX27_SDRAM_BASE_ADDR 0xa0000000
99#define MX27_CSD1_BASE_ADDR 0xb0000000
100
101#define MX27_CS0_BASE_ADDR 0xc0000000
102#define MX27_CS1_BASE_ADDR 0xc8000000
103#define MX27_CS2_BASE_ADDR 0xd0000000
104#define MX27_CS3_BASE_ADDR 0xd2000000
105#define MX27_CS4_BASE_ADDR 0xd4000000
106#define MX27_CS5_BASE_ADDR 0xd6000000
107
108/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
109#define MX27_X_MEMC_BASE_ADDR 0xd8000000
110#define MX27_X_MEMC_SIZE SZ_1M
111#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
112#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
113#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
114#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
115#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
116
117#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
118#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
119#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121
122#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
123
124/* IRAM */
125#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
126
127#define MX27_IO_P2V(x) IMX_IO_P2V(x)
128#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
129
130/* fixed interrupt numbers */
131#include <asm/irq.h>
132#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
133#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
134#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
135#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
136#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
137#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
138#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
139#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
140#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
141#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
142#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
143#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
144#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
145#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
146#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
147#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
148#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
149#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
150#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
151#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
152#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
153#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
154#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
155#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
156#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
157#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
158#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
159#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
160#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
161#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
162#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
163#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
164#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
165#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
166#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
167#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
168#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
169#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
170#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
171#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
172#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
173#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
174#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
175#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
176#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
177#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
178#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
179#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
180#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
181#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
182#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
183#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
184#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
185#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
186#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
187#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
188#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
189#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
190#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
191#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
192#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
193#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
194#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
195
196/* fixed DMA request numbers */
197#define MX27_DMA_REQ_CSPI3_RX 1
198#define MX27_DMA_REQ_CSPI3_TX 2
199#define MX27_DMA_REQ_EXT 3
200#define MX27_DMA_REQ_MSHC 4
201#define MX27_DMA_REQ_SDHC2 6
202#define MX27_DMA_REQ_SDHC1 7
203#define MX27_DMA_REQ_SSI2_RX0 8
204#define MX27_DMA_REQ_SSI2_TX0 9
205#define MX27_DMA_REQ_SSI2_RX1 10
206#define MX27_DMA_REQ_SSI2_TX1 11
207#define MX27_DMA_REQ_SSI1_RX0 12
208#define MX27_DMA_REQ_SSI1_TX0 13
209#define MX27_DMA_REQ_SSI1_RX1 14
210#define MX27_DMA_REQ_SSI1_TX1 15
211#define MX27_DMA_REQ_CSPI2_RX 16
212#define MX27_DMA_REQ_CSPI2_TX 17
213#define MX27_DMA_REQ_CSPI1_RX 18
214#define MX27_DMA_REQ_CSPI1_TX 19
215#define MX27_DMA_REQ_UART4_RX 20
216#define MX27_DMA_REQ_UART4_TX 21
217#define MX27_DMA_REQ_UART3_RX 22
218#define MX27_DMA_REQ_UART3_TX 23
219#define MX27_DMA_REQ_UART2_RX 24
220#define MX27_DMA_REQ_UART2_TX 25
221#define MX27_DMA_REQ_UART1_RX 26
222#define MX27_DMA_REQ_UART1_TX 27
223#define MX27_DMA_REQ_ATA_TX 28
224#define MX27_DMA_REQ_ATA_RCV 29
225#define MX27_DMA_REQ_CSI_STAT 30
226#define MX27_DMA_REQ_CSI_RX 31
227#define MX27_DMA_REQ_UART5_TX 32
228#define MX27_DMA_REQ_UART5_RX 33
229#define MX27_DMA_REQ_UART6_TX 34
230#define MX27_DMA_REQ_UART6_RX 35
231#define MX27_DMA_REQ_SDHC3 36
232#define MX27_DMA_REQ_NFC 37
233
234#ifndef __ASSEMBLY__
235extern int mx27_revision(void);
236#endif
237
238#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx2x.h b/arch/arm/mach-imx/include/mach/mx2x.h
deleted file mode 100644
index 11642f5b224c..000000000000
--- a/arch/arm/mach-imx/include/mach/mx2x.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#ifndef __MACH_MX2x_H__
24#define __MACH_MX2x_H__
25
26/* The following addresses are common between i.MX21 and i.MX27 */
27
28/* Register offsets */
29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define MX2x_AIPI_SIZE SZ_1M
31#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
32#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
33#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
34#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
35#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
36#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
37#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
38#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
39#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
40#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
41#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
42#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
43#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
44#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
45#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
46#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
47#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
48#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
49#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
50#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
51#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
52#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
53#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
54#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
55#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
56#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
57#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
58#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
59#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
60#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
61#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
62#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
63
64#define MX2x_AVIC_BASE_ADDR 0x10040000
65
66#define MX2x_SAHB1_BASE_ADDR 0x80000000
67#define MX2x_SAHB1_SIZE SZ_1M
68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
69
70/* fixed interrupt numbers */
71#include <asm/irq.h>
72#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
73#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
74#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
75#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
76#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
77#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
78#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
79#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
80#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
81#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
82#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
83#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
84#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
85#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
86#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
87#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
88#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
89#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
90#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
91#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
92#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
93#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
94#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
95#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
96#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
97#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
98#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
99#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
100#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
101#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
102#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
103#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
104#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
105#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
106#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
107#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
108#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
109#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
110#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
111#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
112#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
113#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
114#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
115
116/* fixed DMA request numbers */
117#define MX2x_DMA_REQ_CSPI3_RX 1
118#define MX2x_DMA_REQ_CSPI3_TX 2
119#define MX2x_DMA_REQ_EXT 3
120#define MX2x_DMA_REQ_SDHC2 6
121#define MX2x_DMA_REQ_SDHC1 7
122#define MX2x_DMA_REQ_SSI2_RX0 8
123#define MX2x_DMA_REQ_SSI2_TX0 9
124#define MX2x_DMA_REQ_SSI2_RX1 10
125#define MX2x_DMA_REQ_SSI2_TX1 11
126#define MX2x_DMA_REQ_SSI1_RX0 12
127#define MX2x_DMA_REQ_SSI1_TX0 13
128#define MX2x_DMA_REQ_SSI1_RX1 14
129#define MX2x_DMA_REQ_SSI1_TX1 15
130#define MX2x_DMA_REQ_CSPI2_RX 16
131#define MX2x_DMA_REQ_CSPI2_TX 17
132#define MX2x_DMA_REQ_CSPI1_RX 18
133#define MX2x_DMA_REQ_CSPI1_TX 19
134#define MX2x_DMA_REQ_UART4_RX 20
135#define MX2x_DMA_REQ_UART4_TX 21
136#define MX2x_DMA_REQ_UART3_RX 22
137#define MX2x_DMA_REQ_UART3_TX 23
138#define MX2x_DMA_REQ_UART2_RX 24
139#define MX2x_DMA_REQ_UART2_TX 25
140#define MX2x_DMA_REQ_UART1_RX 26
141#define MX2x_DMA_REQ_UART1_TX 27
142#define MX2x_DMA_REQ_CSI_STAT 30
143#define MX2x_DMA_REQ_CSI_RX 31
144
145#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx31.h b/arch/arm/mach-imx/include/mach/mx31.h
deleted file mode 100644
index ee9b1f9215df..000000000000
--- a/arch/arm/mach-imx/include/mach/mx31.h
+++ /dev/null
@@ -1,196 +0,0 @@
1#ifndef __MACH_MX31_H__
2#define __MACH_MX31_H__
3
4/*
5 * IRAM
6 */
7#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
8#define MX31_IRAM_SIZE SZ_16K
9
10#define MX31_L2CC_BASE_ADDR 0x30000000
11#define MX31_L2CC_SIZE SZ_1M
12
13#define MX31_AIPS1_BASE_ADDR 0x43f00000
14#define MX31_AIPS1_SIZE SZ_1M
15#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
16#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
17#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
18#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
19#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
20#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
21#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
22#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
23#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
24#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
25#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
26#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
27#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
28#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
29#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
30#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
31#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
32#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
33#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
34#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
35#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
36#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
37#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
38#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
39#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
40
41#define MX31_SPBA0_BASE_ADDR 0x50000000
42#define MX31_SPBA0_SIZE SZ_1M
43#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
44#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
45#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
46#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
47#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
48#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
49#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
50#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
51#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
52#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
53
54#define MX31_AIPS2_BASE_ADDR 0x53f00000
55#define MX31_AIPS2_SIZE SZ_1M
56#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
57#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
58#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
59#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
60#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
61#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
62#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
63#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
64#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
65#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
66#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
67#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
68#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
69#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
70#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
71#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
72#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
73#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
74#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
75#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
76#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
77
78#define MX31_ROMP_BASE_ADDR 0x60000000
79#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
80#define MX31_ROMP_SIZE SZ_1M
81
82#define MX31_AVIC_BASE_ADDR 0x68000000
83#define MX31_AVIC_SIZE SZ_1M
84
85#define MX31_IPU_MEM_BASE_ADDR 0x70000000
86#define MX31_CSD0_BASE_ADDR 0x80000000
87#define MX31_CSD1_BASE_ADDR 0x90000000
88
89#define MX31_CS0_BASE_ADDR 0xa0000000
90#define MX31_CS1_BASE_ADDR 0xa8000000
91#define MX31_CS2_BASE_ADDR 0xb0000000
92#define MX31_CS3_BASE_ADDR 0xb2000000
93
94#define MX31_CS4_BASE_ADDR 0xb4000000
95#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
96#define MX31_CS4_SIZE SZ_32M
97
98#define MX31_CS5_BASE_ADDR 0xb6000000
99#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
100#define MX31_CS5_SIZE SZ_32M
101
102#define MX31_X_MEMC_BASE_ADDR 0xb8000000
103#define MX31_X_MEMC_SIZE SZ_64K
104#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
105#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
106#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
107#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
108#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
109#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
110
111#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
112#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
113#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
114#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
115
116#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
117
118#define MX31_IO_P2V(x) IMX_IO_P2V(x)
119#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
120
121/*
122 * Interrupt numbers
123 */
124#include <asm/irq.h>
125#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
128#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
129#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
130#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
131#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
132#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
133#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
134#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
135#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
136#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
137#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
138#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
139#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
140#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
141#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
142#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
143#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
144#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
145#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
146#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
147#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
148#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
149#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
150#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
151#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
152#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
153#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
154#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
155#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
156#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
157#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
158#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
159#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
160#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
161#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
162#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
163#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
164#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
165#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
166#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
167#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
168#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
169#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
170#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
171#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
172#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
173#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
174#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
175#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
176#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
177#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
178#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
179#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
180#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
181#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
182
183#define MX31_DMA_REQ_SDHC1 20
184#define MX31_DMA_REQ_SDHC2 21
185#define MX31_DMA_REQ_SSI2_RX1 22
186#define MX31_DMA_REQ_SSI2_TX1 23
187#define MX31_DMA_REQ_SSI2_RX0 24
188#define MX31_DMA_REQ_SSI2_TX0 25
189#define MX31_DMA_REQ_SSI1_RX1 26
190#define MX31_DMA_REQ_SSI1_TX1 27
191#define MX31_DMA_REQ_SSI1_RX0 28
192#define MX31_DMA_REQ_SSI1_TX0 29
193
194#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
195
196#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx35.h b/arch/arm/mach-imx/include/mach/mx35.h
deleted file mode 100644
index 2af5d3a699c7..000000000000
--- a/arch/arm/mach-imx/include/mach/mx35.h
+++ /dev/null
@@ -1,190 +0,0 @@
1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__
3
4/*
5 * IRAM
6 */
7#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
8#define MX35_IRAM_SIZE SZ_128K
9
10#define MX35_L2CC_BASE_ADDR 0x30000000
11#define MX35_L2CC_SIZE SZ_1M
12
13#define MX35_AIPS1_BASE_ADDR 0x43f00000
14#define MX35_AIPS1_SIZE SZ_1M
15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
17#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
25#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
26#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
27#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
28#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
29#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
30#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
31#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
33
34#define MX35_SPBA0_BASE_ADDR 0x50000000
35#define MX35_SPBA0_SIZE SZ_1M
36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
38#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
39#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
40#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
41#define MX35_FEC_BASE_ADDR 0x50038000
42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
43
44#define MX35_AIPS2_BASE_ADDR 0x53f00000
45#define MX35_AIPS2_SIZE SZ_1M
46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
48#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
49#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
50#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
51#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
52#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
53#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
54#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
55#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
56#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
57#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
58#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
59#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
60#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
61#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
62#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
63#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
64#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
65#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
66#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
67#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
68#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
69#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
70/*
71 * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
72 * HS. When host support was implemented only a preliminary document was
73 * available, which told 0x400. This works fine.
74 */
75#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
76
77#define MX35_ROMP_BASE_ADDR 0x60000000
78#define MX35_ROMP_SIZE SZ_1M
79
80#define MX35_AVIC_BASE_ADDR 0x68000000
81#define MX35_AVIC_SIZE SZ_1M
82
83/*
84 * Memory regions and CS
85 */
86#define MX35_IPU_MEM_BASE_ADDR 0x70000000
87#define MX35_CSD0_BASE_ADDR 0x80000000
88#define MX35_CSD1_BASE_ADDR 0x90000000
89
90#define MX35_CS0_BASE_ADDR 0xa0000000
91#define MX35_CS1_BASE_ADDR 0xa8000000
92#define MX35_CS2_BASE_ADDR 0xb0000000
93#define MX35_CS3_BASE_ADDR 0xb2000000
94
95#define MX35_CS4_BASE_ADDR 0xb4000000
96#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
97#define MX35_CS4_SIZE SZ_32M
98
99#define MX35_CS5_BASE_ADDR 0xb6000000
100#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
101#define MX35_CS5_SIZE SZ_32M
102
103/*
104 * NAND, SDRAM, WEIM, M3IF, EMI controllers
105 */
106#define MX35_X_MEMC_BASE_ADDR 0xb8000000
107#define MX35_X_MEMC_SIZE SZ_64K
108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
110#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
111#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
112#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
113
114#define MX35_NFC_BASE_ADDR 0xbb000000
115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
116
117#define MX35_IO_P2V(x) IMX_IO_P2V(x)
118#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
119
120/*
121 * Interrupt numbers
122 */
123#include <asm/irq.h>
124#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
125#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
128#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
129#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
130#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
131#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
132#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
133#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
134#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
135#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
136#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
137#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
138#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
139#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
140#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
141#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
142#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
143#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
144#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
145#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
146#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
147#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
148#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
149#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
150#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
151#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
152#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
153#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
154#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
155#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
156#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
157#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
158#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
159#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
160#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
161#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
162#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
163#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
164#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
165#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
166#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
167#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
168#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
169#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
170#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
171#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
172#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
173#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
174#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
175#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
176#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
177#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
178
179#define MX35_DMA_REQ_SSI2_RX1 22
180#define MX35_DMA_REQ_SSI2_TX1 23
181#define MX35_DMA_REQ_SSI2_RX0 24
182#define MX35_DMA_REQ_SSI2_TX0 25
183#define MX35_DMA_REQ_SSI1_RX1 26
184#define MX35_DMA_REQ_SSI1_TX1 27
185#define MX35_DMA_REQ_SSI1_RX0 28
186#define MX35_DMA_REQ_SSI1_TX0 29
187
188#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
189
190#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx3x.h b/arch/arm/mach-imx/include/mach/mx3x.h
deleted file mode 100644
index 96fb4fbc8ad7..000000000000
--- a/arch/arm/mach-imx/include/mach/mx3x.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_MX3x_H__
12#define __MACH_MX3x_H__
13
14/*
15 * MX31 memory map:
16 *
17 * Virt Phys Size What
18 * ---------------------------------------------------------------------------
19 * FC000000 43F00000 1M AIPS 1
20 * FC100000 50000000 1M SPBA
21 * FC200000 53F00000 1M AIPS 2
22 * FC500000 60000000 128M ROMPATCH
23 * FC400000 68000000 128M AVIC
24 * 70000000 256M IPU (MAX M2)
25 * 80000000 256M CSD0 SDRAM/DDR
26 * 90000000 256M CSD1 SDRAM/DDR
27 * A0000000 128M CS0 Flash
28 * A8000000 128M CS1 Flash
29 * B0000000 32M CS2
30 * B2000000 32M CS3
31 * F4000000 B4000000 32M CS4
32 * B6000000 32M CS5
33 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
34 * C0000000 64M PCMCIA/CF
35 */
36
37/*
38 * L2CC
39 */
40#define MX3x_L2CC_BASE_ADDR 0x30000000
41#define MX3x_L2CC_SIZE SZ_1M
42
43/*
44 * AIPS 1
45 */
46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
47#define MX3x_AIPS1_SIZE SZ_1M
48#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
49#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
50#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
51#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
52#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
53#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
54#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
55#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
56#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
57#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
58#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
59#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
60#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
61#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
62#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
63#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
64#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
65#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
66
67/*
68 * SPBA global module enabled #0
69 */
70#define MX3x_SPBA0_BASE_ADDR 0x50000000
71#define MX3x_SPBA0_SIZE SZ_1M
72#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
73#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
74#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
75#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
76#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
77#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
78
79/*
80 * AIPS 2
81 */
82#define MX3x_AIPS2_BASE_ADDR 0x53f00000
83#define MX3x_AIPS2_SIZE SZ_1M
84#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
85#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
86#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
87#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
88#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
89#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
90#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
91#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
92#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
93#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
94#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
95#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
96#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
97#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
98#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
99#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
100
101/*
102 * ROMP and AVIC
103 */
104#define MX3x_ROMP_BASE_ADDR 0x60000000
105#define MX3x_ROMP_SIZE SZ_1M
106
107#define MX3x_AVIC_BASE_ADDR 0x68000000
108#define MX3x_AVIC_SIZE SZ_1M
109
110/*
111 * Memory regions and CS
112 */
113#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
114#define MX3x_CSD0_BASE_ADDR 0x80000000
115#define MX3x_CSD1_BASE_ADDR 0x90000000
116
117#define MX3x_CS0_BASE_ADDR 0xa0000000
118#define MX3x_CS1_BASE_ADDR 0xa8000000
119#define MX3x_CS2_BASE_ADDR 0xb0000000
120#define MX3x_CS3_BASE_ADDR 0xb2000000
121
122#define MX3x_CS4_BASE_ADDR 0xb4000000
123#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
124#define MX3x_CS4_SIZE SZ_32M
125
126#define MX3x_CS5_BASE_ADDR 0xb6000000
127#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
128#define MX3x_CS5_SIZE SZ_32M
129
130/*
131 * NAND, SDRAM, WEIM, M3IF, EMI controllers
132 */
133#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
134#define MX3x_X_MEMC_SIZE SZ_64K
135#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
136#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
137#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
138#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
139#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
140
141#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
142
143/*
144 * Interrupt numbers
145 */
146#include <asm/irq.h>
147#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
148#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
149#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
150#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
151#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
152#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
153#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
154#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
155#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
156#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
157#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
158#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
159#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
160#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
161#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
162#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
163#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
164#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
165#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
166#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
167#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
168#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
169#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
170#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
171#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
172#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
173#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
174#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
175#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
176#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
177#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
178#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
179#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
180#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
181#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
182#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
183#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
184#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
185
186#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
187
188/* Mandatory defines used globally */
189
190#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
191extern int mx35_revision(void);
192extern int mx31_revision(void);
193#endif
194
195#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx50.h b/arch/arm/mach-imx/include/mach/mx50.h
deleted file mode 100644
index 09ac19c1570c..000000000000
--- a/arch/arm/mach-imx/include/mach/mx50.h
+++ /dev/null
@@ -1,290 +0,0 @@
1#ifndef __MACH_MX50_H__
2#define __MACH_MX50_H__
3
4/*
5 * IROM
6 */
7#define MX50_IROM_BASE_ADDR 0x0
8#define MX50_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX50_TZIC_BASE_ADDR 0x0fffc000
12#define MX50_TZIC_SIZE SZ_16K
13
14/*
15 * IRAM
16 */
17#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
18#define MX50_IRAM_PARTITIONS 16
19#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
20
21/*
22 * Databahn
23 */
24#define MX50_DATABAHN_BASE_ADDR 0x14000000
25
26/*
27 * Graphics Memory of GPU
28 */
29#define MX50_GPU2D_BASE_ADDR 0x20000000
30
31#define MX50_DEBUG_BASE_ADDR 0x40000000
32#define MX50_DEBUG_SIZE SZ_1M
33#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
34#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
35#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
36#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
37#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
38#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
39#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
40#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
41
42#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
43#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
44#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
45#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
46#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
47#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
48#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
49#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
50#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
51#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
52#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
53#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
54#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
55#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
56
57/*
58 * SPBA global module enabled #0
59 */
60#define MX50_SPBA0_BASE_ADDR 0x50000000
61#define MX50_SPBA0_SIZE SZ_1M
62
63#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
64#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
65#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
66#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
67#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
68#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
69#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
70
71/*
72 * AIPS 1
73 */
74#define MX50_AIPS1_BASE_ADDR 0x53f00000
75#define MX50_AIPS1_SIZE SZ_1M
76
77#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
78#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
79#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
80#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
81#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
82#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
83#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
84#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
85#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
86#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
87#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
88#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
89#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
90#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
91#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
92#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
93#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
94#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
95#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
96#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
97#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
98#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
99
100#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
101#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
102
103/*
104 * AIPS 2
105 */
106#define MX50_AIPS2_BASE_ADDR 0x63f00000
107#define MX50_AIPS2_SIZE SZ_1M
108
109#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
110#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
111#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
112#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
113#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
114#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
115#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
116#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
117#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
118#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
119#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
120#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
121#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
122#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
123#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
124#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
125#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
126
127/*
128 * Memory regions and CS
129 */
130#define MX50_CSD0_BASE_ADDR 0x70000000
131#define MX50_CSD1_BASE_ADDR 0xb0000000
132#define MX50_CS0_BASE_ADDR 0xf0000000
133
134#define MX50_IO_P2V(x) IMX_IO_P2V(x)
135#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
136
137/*
138 * defines for SPBA modules
139 */
140#define MX50_SPBA_SDHC1 0x04
141#define MX50_SPBA_SDHC2 0x08
142#define MX50_SPBA_UART3 0x0c
143#define MX50_SPBA_CSPI1 0x10
144#define MX50_SPBA_SSI2 0x14
145#define MX50_SPBA_SDHC3 0x20
146#define MX50_SPBA_SDHC4 0x24
147#define MX50_SPBA_SPDIF 0x28
148#define MX50_SPBA_ATA 0x30
149#define MX50_SPBA_SLIM 0x34
150#define MX50_SPBA_HSI2C 0x38
151#define MX50_SPBA_CTRL 0x3c
152
153/*
154 * DMA request assignments
155 */
156#define MX50_DMA_REQ_GPC 1
157#define MX50_DMA_REQ_ATA_UART4_RX 2
158#define MX50_DMA_REQ_ATA_UART4_TX 3
159#define MX50_DMA_REQ_CSPI1_RX 6
160#define MX50_DMA_REQ_CSPI1_TX 7
161#define MX50_DMA_REQ_CSPI2_RX 8
162#define MX50_DMA_REQ_CSPI2_TX 9
163#define MX50_DMA_REQ_I2C3_SDHC3 10
164#define MX50_DMA_REQ_SDHC4 11
165#define MX50_DMA_REQ_UART2_FIRI_RX 12
166#define MX50_DMA_REQ_UART2_FIRI_TX 13
167#define MX50_DMA_REQ_EXT0 14
168#define MX50_DMA_REQ_EXT1 15
169#define MX50_DMA_REQ_UART5_RX 16
170#define MX50_DMA_REQ_UART5_TX 17
171#define MX50_DMA_REQ_UART1_RX 18
172#define MX50_DMA_REQ_UART1_TX 19
173#define MX50_DMA_REQ_I2C1_SDHC1 20
174#define MX50_DMA_REQ_I2C2_SDHC2 21
175#define MX50_DMA_REQ_SSI2_RX2 22
176#define MX50_DMA_REQ_SSI2_TX2 23
177#define MX50_DMA_REQ_SSI2_RX1 24
178#define MX50_DMA_REQ_SSI2_TX1 25
179#define MX50_DMA_REQ_SSI1_RX2 26
180#define MX50_DMA_REQ_SSI1_TX2 27
181#define MX50_DMA_REQ_SSI1_RX1 28
182#define MX50_DMA_REQ_SSI1_TX1 29
183#define MX50_DMA_REQ_CSPI_RX 38
184#define MX50_DMA_REQ_CSPI_TX 39
185#define MX50_DMA_REQ_UART3_RX 42
186#define MX50_DMA_REQ_UART3_TX 43
187
188/*
189 * Interrupt numbers
190 */
191#include <asm/irq.h>
192#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
193#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
194#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
195#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
196#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
197#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
198#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
199#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
200#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
201#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
202#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
203#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
204#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
205#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
206#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
207#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
208#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
209#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
210#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
211#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
212#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
213#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
214#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
215#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
216#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
217#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
218#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
219#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
220#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
221#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
222#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
223#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
224#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
225#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
226#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
227#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
228#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
229#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
230#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
231#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
232#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
233#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
234#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
235#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
236#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
237#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
238#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
239#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
240#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
241#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
242#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
243#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
244#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
245#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
246#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
247#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
248#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
249#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
250#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
251#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
252#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
253#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
254#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
255#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
256#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
257#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
258#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
259#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
260#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
261#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
262#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
263#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
264#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
265#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
266#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
267#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
268#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
269#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
270#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
271#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
272#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
273#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
274#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
275#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
276#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
277#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
278#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
279#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
280#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
281#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
282#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
283#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
284#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
285
286#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
287extern int mx50_revision(void);
288#endif
289
290#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx51.h b/arch/arm/mach-imx/include/mach/mx51.h
deleted file mode 100644
index af844f76261a..000000000000
--- a/arch/arm/mach-imx/include/mach/mx51.h
+++ /dev/null
@@ -1,346 +0,0 @@
1#ifndef __MACH_MX51_H__
2#define __MACH_MX51_H__
3
4/*
5 * IROM
6 */
7#define MX51_IROM_BASE_ADDR 0x0
8#define MX51_IROM_SIZE SZ_64K
9
10/*
11 * IRAM
12 */
13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
14#define MX51_IRAM_PARTITIONS 16
15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
16
17#define MX51_GPU_BASE_ADDR 0x20000000
18#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
20
21/*
22 * SPBA global module enabled #0
23 */
24#define MX51_SPBA0_BASE_ADDR 0x70000000
25#define MX51_SPBA0_SIZE SZ_1M
26
27#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
28#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
29#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
30#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
31#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
32#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
33#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
34#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
35#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
36#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
37#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
38#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
39
40/*
41 * AIPS 1
42 */
43#define MX51_AIPS1_BASE_ADDR 0x73f00000
44#define MX51_AIPS1_SIZE SZ_1M
45
46#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
47#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
48#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
49#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
50#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
51#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
52#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
53#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
54#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
55#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
56#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
57#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
58#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
59#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
60#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
61#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
62#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
63#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
64#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
65#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
66#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
67#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
68#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
69
70/*
71 * AIPS 2
72 */
73#define MX51_AIPS2_BASE_ADDR 0x83f00000
74#define MX51_AIPS2_SIZE SZ_1M
75
76#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
77#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
78#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
79#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
80#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
81#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
82#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
83#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
84#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
85#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
86#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
87#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
88#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
89#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
90#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
91#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
92#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
93#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
94#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
95#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
96#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
97#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
98#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
99#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
100#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
101#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
102#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
103#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
104#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
105#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
106#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
107#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
108
109#define MX51_CSD0_BASE_ADDR 0x90000000
110#define MX51_CSD1_BASE_ADDR 0xa0000000
111#define MX51_CS0_BASE_ADDR 0xb0000000
112#define MX51_CS1_BASE_ADDR 0xb8000000
113#define MX51_CS2_BASE_ADDR 0xc0000000
114#define MX51_CS3_BASE_ADDR 0xc8000000
115#define MX51_CS4_BASE_ADDR 0xcc000000
116#define MX51_CS5_BASE_ADDR 0xce000000
117
118/*
119 * NFC
120 */
121#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
122#define MX51_NFC_AXI_SIZE SZ_64K
123
124#define MX51_GPU2D_BASE_ADDR 0xd0000000
125#define MX51_TZIC_BASE_ADDR 0xe0000000
126#define MX51_TZIC_SIZE SZ_16K
127
128#define MX51_IO_P2V(x) IMX_IO_P2V(x)
129#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
130
131/*
132 * defines for SPBA modules
133 */
134#define MX51_SPBA_SDHC1 0x04
135#define MX51_SPBA_SDHC2 0x08
136#define MX51_SPBA_UART3 0x0c
137#define MX51_SPBA_CSPI1 0x10
138#define MX51_SPBA_SSI2 0x14
139#define MX51_SPBA_SDHC3 0x20
140#define MX51_SPBA_SDHC4 0x24
141#define MX51_SPBA_SPDIF 0x28
142#define MX51_SPBA_ATA 0x30
143#define MX51_SPBA_SLIM 0x34
144#define MX51_SPBA_HSI2C 0x38
145#define MX51_SPBA_CTRL 0x3c
146
147/*
148 * Defines for modules using static and dynamic DMA channels
149 */
150#define MX51_MXC_DMA_CHANNEL_IRAM 30
151#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
152#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
153#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
154#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
155#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
156#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
157#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
162#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
163#ifdef CONFIG_SDMA_IRAM
164#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
165#else /*CONFIG_SDMA_IRAM */
166#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
167#endif /*CONFIG_SDMA_IRAM */
168#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
169#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
170#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
171#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
172#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
173#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
174#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
175#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
176#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
177
178#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
179
180/*
181 * DMA request assignments
182 */
183#define MX51_DMA_REQ_VPU 0
184#define MX51_DMA_REQ_GPC 1
185#define MX51_DMA_REQ_ATA_RX 2
186#define MX51_DMA_REQ_ATA_TX 3
187#define MX51_DMA_REQ_ATA_TX_END 4
188#define MX51_DMA_REQ_SLIM_B 5
189#define MX51_DMA_REQ_CSPI1_RX 6
190#define MX51_DMA_REQ_CSPI1_TX 7
191#define MX51_DMA_REQ_CSPI2_RX 8
192#define MX51_DMA_REQ_CSPI2_TX 9
193#define MX51_DMA_REQ_HS_I2C_TX 10
194#define MX51_DMA_REQ_HS_I2C_RX 11
195#define MX51_DMA_REQ_FIRI_RX 12
196#define MX51_DMA_REQ_FIRI_TX 13
197#define MX51_DMA_REQ_EXTREQ1 14
198#define MX51_DMA_REQ_GPU 15
199#define MX51_DMA_REQ_UART2_RX 16
200#define MX51_DMA_REQ_UART2_TX 17
201#define MX51_DMA_REQ_UART1_RX 18
202#define MX51_DMA_REQ_UART1_TX 19
203#define MX51_DMA_REQ_SDHC1 20
204#define MX51_DMA_REQ_SDHC2 21
205#define MX51_DMA_REQ_SSI2_RX1 22
206#define MX51_DMA_REQ_SSI2_TX1 23
207#define MX51_DMA_REQ_SSI2_RX0 24
208#define MX51_DMA_REQ_SSI2_TX0 25
209#define MX51_DMA_REQ_SSI1_RX1 26
210#define MX51_DMA_REQ_SSI1_TX1 27
211#define MX51_DMA_REQ_SSI1_RX0 28
212#define MX51_DMA_REQ_SSI1_TX0 29
213#define MX51_DMA_REQ_EMI_RD 30
214#define MX51_DMA_REQ_CTI2_0 31
215#define MX51_DMA_REQ_EMI_WR 32
216#define MX51_DMA_REQ_CTI2_1 33
217#define MX51_DMA_REQ_EPIT2 34
218#define MX51_DMA_REQ_SSI3_RX1 35
219#define MX51_DMA_REQ_IPU 36
220#define MX51_DMA_REQ_SSI3_TX1 37
221#define MX51_DMA_REQ_CSPI_RX 38
222#define MX51_DMA_REQ_CSPI_TX 39
223#define MX51_DMA_REQ_SDHC3 40
224#define MX51_DMA_REQ_SDHC4 41
225#define MX51_DMA_REQ_SLIM_B_TX 42
226#define MX51_DMA_REQ_UART3_RX 43
227#define MX51_DMA_REQ_UART3_TX 44
228#define MX51_DMA_REQ_SPDIF 45
229#define MX51_DMA_REQ_SSI3_RX0 46
230#define MX51_DMA_REQ_SSI3_TX0 47
231
232/*
233 * Interrupt numbers
234 */
235#include <asm/irq.h>
236#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
237#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
238#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
239#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
240#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
241#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
242#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
243#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
244#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
245#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
246#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
247#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
248#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
249#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
250#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
251#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
252#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
253#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
254#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
255#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
256#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
257#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
258#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
259#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
260#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
261#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
262#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
263#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
264#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
265#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
266#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
267#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
268#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
269#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
270#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
271#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
272#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
273#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
274#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
275#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
276#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
277#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
278#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
279#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
280#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
281#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
282#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
283#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
284#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
285#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
286#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
287#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
288#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
289#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
290#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
291#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
292#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
293#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
294#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
295#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
296#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
297#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
298#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
299#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
300#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
301#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
302#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
303#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
304#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
305#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
306#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
307#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
308#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
309#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
310#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
311#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
312#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
313#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
314#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
315#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
316#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
317#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
318#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
319#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
320#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
321#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
322#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
323#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
324#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
325#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
326#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
327#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
328#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
329#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
330#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
331#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
332#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
333#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
334#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
335#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
336#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
337#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
338#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
339#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
340
341#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
342extern int mx51_revision(void);
343extern void mx51_display_revision(void);
344#endif
345
346#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx53.h b/arch/arm/mach-imx/include/mach/mx53.h
deleted file mode 100644
index f829d1c22501..000000000000
--- a/arch/arm/mach-imx/include/mach/mx53.h
+++ /dev/null
@@ -1,342 +0,0 @@
1#ifndef __MACH_MX53_H__
2#define __MACH_MX53_H__
3
4/*
5 * IROM
6 */
7#define MX53_IROM_BASE_ADDR 0x0
8#define MX53_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX53_TZIC_BASE_ADDR 0x0FFFC000
12#define MX53_TZIC_SIZE SZ_16K
13
14/*
15 * AHCI SATA
16 */
17#define MX53_SATA_BASE_ADDR 0x10000000
18
19/*
20 * NFC
21 */
22#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
23#define MX53_NFC_AXI_SIZE SZ_64K
24
25/*
26 * IRAM
27 */
28#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
29#define MX53_IRAM_PARTITIONS 16
30#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
31
32/*
33 * Graphics Memory of GPU
34 */
35#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
36#define MX53_GPU2D_BASE_ADDR 0x20000000
37#define MX53_GPU_BASE_ADDR 0x30000000
38#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
39
40#define MX53_DEBUG_BASE_ADDR 0x40000000
41#define MX53_DEBUG_SIZE SZ_1M
42#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
43#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
44#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
45#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
46#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
47#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
48#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
49#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
50
51/*
52 * SPBA global module enabled #0
53 */
54#define MX53_SPBA0_BASE_ADDR 0x50000000
55#define MX53_SPBA0_SIZE SZ_1M
56
57#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
58#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
59#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
60#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
61#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
62#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
63#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
64#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
65#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
66#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
67#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
68#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
69#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
70
71/*
72 * AIPS 1
73 */
74#define MX53_AIPS1_BASE_ADDR 0x53F00000
75#define MX53_AIPS1_SIZE SZ_1M
76
77#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
78#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
79#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
80#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
81#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
82#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
83#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
84#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
85#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
86#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
87#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
88#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
89#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
90#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
91#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
92#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
93#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
94#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
95#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
96#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
97#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
98#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
99#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
100#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
101#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
102#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
103
104/*
105 * AIPS 2
106 */
107#define MX53_AIPS2_BASE_ADDR 0x63F00000
108#define MX53_AIPS2_SIZE SZ_1M
109
110#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
111#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
112#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
113#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
114#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
115#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
116#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
117#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
118#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
119#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
120#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
121#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
122#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
123#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
124#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
125#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
126#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
127#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
128#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
129#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
130#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
131#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
132#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
133#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
134#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
135#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
136#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
137#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
138#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
139#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
140#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
141#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
142#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
143#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
144#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
145
146/*
147 * Memory regions and CS
148 */
149#define MX53_CSD0_BASE_ADDR 0x70000000
150#define MX53_CSD1_BASE_ADDR 0xB0000000
151#define MX53_CS0_BASE_ADDR 0xF0000000
152#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
153#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
154#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
155#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
156#define MX53_CS3_BASE_ADDR 0xF6000000
157
158#define MX53_IO_P2V(x) IMX_IO_P2V(x)
159#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
160
161/*
162 * defines for SPBA modules
163 */
164#define MX53_SPBA_SDHC1 0x04
165#define MX53_SPBA_SDHC2 0x08
166#define MX53_SPBA_UART3 0x0C
167#define MX53_SPBA_CSPI1 0x10
168#define MX53_SPBA_SSI2 0x14
169#define MX53_SPBA_SDHC3 0x20
170#define MX53_SPBA_SDHC4 0x24
171#define MX53_SPBA_SPDIF 0x28
172#define MX53_SPBA_ATA 0x30
173#define MX53_SPBA_SLIM 0x34
174#define MX53_SPBA_HSI2C 0x38
175#define MX53_SPBA_CTRL 0x3C
176
177/*
178 * DMA request assignments
179 */
180#define MX53_DMA_REQ_SSI3_TX0 47
181#define MX53_DMA_REQ_SSI3_RX0 46
182#define MX53_DMA_REQ_SSI3_TX1 45
183#define MX53_DMA_REQ_SSI3_RX1 44
184#define MX53_DMA_REQ_UART3_TX 43
185#define MX53_DMA_REQ_UART3_RX 42
186#define MX53_DMA_REQ_ESAI_TX 41
187#define MX53_DMA_REQ_ESAI_RX 40
188#define MX53_DMA_REQ_CSPI_TX 39
189#define MX53_DMA_REQ_CSPI_RX 38
190#define MX53_DMA_REQ_ASRC_DMA6 37
191#define MX53_DMA_REQ_ASRC_DMA5 36
192#define MX53_DMA_REQ_ASRC_DMA4 35
193#define MX53_DMA_REQ_ASRC_DMA3 34
194#define MX53_DMA_REQ_ASRC_DMA2 33
195#define MX53_DMA_REQ_ASRC_DMA1 32
196#define MX53_DMA_REQ_EMI_WR 31
197#define MX53_DMA_REQ_EMI_RD 30
198#define MX53_DMA_REQ_SSI1_TX0 29
199#define MX53_DMA_REQ_SSI1_RX0 28
200#define MX53_DMA_REQ_SSI1_TX1 27
201#define MX53_DMA_REQ_SSI1_RX1 26
202#define MX53_DMA_REQ_SSI2_TX0 25
203#define MX53_DMA_REQ_SSI2_RX0 24
204#define MX53_DMA_REQ_SSI2_TX1 23
205#define MX53_DMA_REQ_SSI2_RX1 22
206#define MX53_DMA_REQ_I2C2_SDHC2 21
207#define MX53_DMA_REQ_I2C1_SDHC1 20
208#define MX53_DMA_REQ_UART1_TX 19
209#define MX53_DMA_REQ_UART1_RX 18
210#define MX53_DMA_REQ_UART5_TX 17
211#define MX53_DMA_REQ_UART5_RX 16
212#define MX53_DMA_REQ_SPDIF_TX 15
213#define MX53_DMA_REQ_SPDIF_RX 14
214#define MX53_DMA_REQ_UART2_FIRI_TX 13
215#define MX53_DMA_REQ_UART2_FIRI_RX 12
216#define MX53_DMA_REQ_SDHC4 11
217#define MX53_DMA_REQ_I2C3_SDHC3 10
218#define MX53_DMA_REQ_CSPI2_TX 9
219#define MX53_DMA_REQ_CSPI2_RX 8
220#define MX53_DMA_REQ_CSPI1_TX 7
221#define MX53_DMA_REQ_CSPI1_RX 6
222#define MX53_DMA_REQ_IPU 5
223#define MX53_DMA_REQ_ATA_TX_END 4
224#define MX53_DMA_REQ_ATA_UART4_TX 3
225#define MX53_DMA_REQ_ATA_UART4_RX 2
226#define MX53_DMA_REQ_GPC 1
227#define MX53_DMA_REQ_VPU 0
228
229/*
230 * Interrupt numbers
231 */
232#include <asm/irq.h>
233#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
234#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
235#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
236#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
237#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
238#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
239#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
240#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
241#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
242#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
243#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
244#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
245#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
246#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
247#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
248#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
249#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
250#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
251#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
252#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
253#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
254#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
255#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
256#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
257#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
258#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
259#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
260#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
261#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
262#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
263#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
264#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
265#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
266#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
267#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
268#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
269#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
270#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
271#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
272#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
273#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
274#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
275#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
276#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
277#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
278#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
279#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
280#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
281#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
282#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
283#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
284#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
285#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
286#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
287#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
288#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
289#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
290#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
291#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
292#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
293#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
294#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
295#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
296#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
297#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
298#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
299#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
300#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
301#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
302#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
303#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
304#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
305#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
306#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
307#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
308#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
309#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
310#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
311#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
312#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
313#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
314#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
315#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
316#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
317#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
318#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
319#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
320#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
321#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
322#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
323#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
324#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
325#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
326#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
327#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
328#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
329#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
330#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
331#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
332#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
333#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
334#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
335#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
336#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
337#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
338#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
339#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
340#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
341
342#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx6q.h b/arch/arm/mach-imx/include/mach/mx6q.h
deleted file mode 100644
index f7e7dbac8f4b..000000000000
--- a/arch/arm/mach-imx/include/mach/mx6q.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __MACH_MX6Q_H__
14#define __MACH_MX6Q_H__
15
16#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
17#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
18
19/*
20 * The following are the blocks that need to be statically mapped.
21 * For other blocks, the base address really should be retrieved from
22 * device tree.
23 */
24#define MX6Q_SCU_BASE_ADDR 0x00a00000
25#define MX6Q_SCU_SIZE 0x1000
26#define MX6Q_CCM_BASE_ADDR 0x020c4000
27#define MX6Q_CCM_SIZE 0x4000
28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29#define MX6Q_ANATOP_SIZE 0x1000
30#define MX6Q_UART2_BASE_ADDR 0x021e8000
31#define MX6Q_UART2_SIZE 0x4000
32#define MX6Q_UART4_BASE_ADDR 0x021f0000
33#define MX6Q_UART4_SIZE 0x4000
34
35#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mxc.h b/arch/arm/mach-imx/include/mach/mxc.h
deleted file mode 100644
index d78298366a91..000000000000
--- a/arch/arm/mach-imx/include/mach/mxc.h
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_H__
21#define __ASM_ARCH_MXC_H__
22
23#include <linux/types.h>
24
25#ifndef __ASM_ARCH_MXC_HARDWARE_H__
26#error "Do not include directly."
27#endif
28
29#define MXC_CPU_MX1 1
30#define MXC_CPU_MX21 21
31#define MXC_CPU_MX25 25
32#define MXC_CPU_MX27 27
33#define MXC_CPU_MX31 31
34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53
38
39#define IMX_CHIP_REVISION_1_0 0x10
40#define IMX_CHIP_REVISION_1_1 0x11
41#define IMX_CHIP_REVISION_1_2 0x12
42#define IMX_CHIP_REVISION_1_3 0x13
43#define IMX_CHIP_REVISION_2_0 0x20
44#define IMX_CHIP_REVISION_2_1 0x21
45#define IMX_CHIP_REVISION_2_2 0x22
46#define IMX_CHIP_REVISION_2_3 0x23
47#define IMX_CHIP_REVISION_3_0 0x30
48#define IMX_CHIP_REVISION_3_1 0x31
49#define IMX_CHIP_REVISION_3_2 0x32
50#define IMX_CHIP_REVISION_3_3 0x33
51#define IMX_CHIP_REVISION_UNKNOWN 0xff
52
53#ifndef __ASSEMBLY__
54extern unsigned int __mxc_cpu_type;
55#endif
56
57#ifdef CONFIG_SOC_IMX1
58# ifdef mxc_cpu_type
59# undef mxc_cpu_type
60# define mxc_cpu_type __mxc_cpu_type
61# else
62# define mxc_cpu_type MXC_CPU_MX1
63# endif
64# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
65#else
66# define cpu_is_mx1() (0)
67#endif
68
69#ifdef CONFIG_SOC_IMX21
70# ifdef mxc_cpu_type
71# undef mxc_cpu_type
72# define mxc_cpu_type __mxc_cpu_type
73# else
74# define mxc_cpu_type MXC_CPU_MX21
75# endif
76# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
77#else
78# define cpu_is_mx21() (0)
79#endif
80
81#ifdef CONFIG_SOC_IMX25
82# ifdef mxc_cpu_type
83# undef mxc_cpu_type
84# define mxc_cpu_type __mxc_cpu_type
85# else
86# define mxc_cpu_type MXC_CPU_MX25
87# endif
88# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
89#else
90# define cpu_is_mx25() (0)
91#endif
92
93#ifdef CONFIG_SOC_IMX27
94# ifdef mxc_cpu_type
95# undef mxc_cpu_type
96# define mxc_cpu_type __mxc_cpu_type
97# else
98# define mxc_cpu_type MXC_CPU_MX27
99# endif
100# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
101#else
102# define cpu_is_mx27() (0)
103#endif
104
105#ifdef CONFIG_SOC_IMX31
106# ifdef mxc_cpu_type
107# undef mxc_cpu_type
108# define mxc_cpu_type __mxc_cpu_type
109# else
110# define mxc_cpu_type MXC_CPU_MX31
111# endif
112# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
113#else
114# define cpu_is_mx31() (0)
115#endif
116
117#ifdef CONFIG_SOC_IMX35
118# ifdef mxc_cpu_type
119# undef mxc_cpu_type
120# define mxc_cpu_type __mxc_cpu_type
121# else
122# define mxc_cpu_type MXC_CPU_MX35
123# endif
124# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
125#else
126# define cpu_is_mx35() (0)
127#endif
128
129#ifdef CONFIG_SOC_IMX50
130# ifdef mxc_cpu_type
131# undef mxc_cpu_type
132# define mxc_cpu_type __mxc_cpu_type
133# else
134# define mxc_cpu_type MXC_CPU_MX50
135# endif
136# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
137#else
138# define cpu_is_mx50() (0)
139#endif
140
141#ifdef CONFIG_SOC_IMX51
142# ifdef mxc_cpu_type
143# undef mxc_cpu_type
144# define mxc_cpu_type __mxc_cpu_type
145# else
146# define mxc_cpu_type MXC_CPU_MX51
147# endif
148# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
149#else
150# define cpu_is_mx51() (0)
151#endif
152
153#ifdef CONFIG_SOC_IMX53
154# ifdef mxc_cpu_type
155# undef mxc_cpu_type
156# define mxc_cpu_type __mxc_cpu_type
157# else
158# define mxc_cpu_type MXC_CPU_MX53
159# endif
160# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
161#else
162# define cpu_is_mx53() (0)
163#endif
164
165#ifndef __ASSEMBLY__
166
167struct cpu_op {
168 u32 cpu_rate;
169};
170
171int tzic_enable_wake(void);
172
173extern struct cpu_op *(*get_cpu_op)(int *op);
174#endif
175
176#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
177#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
178
179#endif /* __ASM_ARCH_MXC_H__ */
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