Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc clock driver changes from Olof Johansson:
 "The new clock subsystem was merged in linux-3.4 without any users,
  this now moves the first three platforms over to it: imx, mxs and
  spear.

  The series also contains the changes for the clock subsystem itself,
  since Mike preferred to have it together with the platforms that
  require these changes, in order to avoid interdependencies and
  conflicts."

Fix up trivial conflicts in arch/arm/mach-kirkwood/common.c (code
removed in one branch, added OF support in another) and
drivers/dma/imx-sdma.c (independent changes next to each other).

* tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits)
  clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
  clk: Provide dummy clk_unregister()
  SPEAr: Update defconfigs
  SPEAr: Add SMI NOR partition info in dts files
  SPEAr: Switch to common clock framework
  SPEAr: Call clk_prepare() before calling clk_enable
  SPEAr: clk: Add General Purpose Timer Synthesizer clock
  SPEAr: clk: Add Fractional Synthesizer clock
  SPEAr: clk: Add Auxiliary Synthesizer clock
  SPEAr: clk: Add VCO-PLL Synthesizer clock
  SPEAr: Add DT bindings for SPEAr's timer
  ARM i.MX: remove now unused clock files
  ARM: i.MX6: implement clocks using common clock framework
  ARM i.MX35: implement clocks using common clock framework
  ARM i.MX5: implement clocks using common clock framework
  ARM: Kirkwood: Replace clock gating
  ARM: Orion: Audio: Add clk/clkdev support
  ARM: Orion: PCIE: Add support for clk
  ARM: Orion: XOR: Add support for clk
  ARM: Orion: CESA: Add support for clk
  ...

1 files changed, 147 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
new file mode 100644
index 000000000000..e2ed4160f329
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/**
+ * struct clk_pfd - IMX PFD clock
+ * @clk_hw:     clock source
+ * @reg:        PFD register address
+ * @idx:        the index of PFD encoded in the register
+ *
+ * PFD clock found on i.MX6 series.  Each register for PFD has 4 clk_pfd
+ * data encoded, and member idx is used to specify the one.  And each
+ * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
+ */
+struct clk_pfd {
+        struct clk_hw   hw;
+        void __iomem    *reg;
+        u8              idx;
+};
+
+#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
+
+#define SET     0x4
+#define CLR     0x8
+#define OTG     0xc
+
+static int clk_pfd_enable(struct clk_hw *hw)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+
+        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
+
+        return 0;
+}
+
+static void clk_pfd_disable(struct clk_hw *hw)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+
+        writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
+}
+
+static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+        u64 tmp = parent_rate;
+        u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+        tmp *= 18;
+        do_div(tmp, frac);
+
+        return tmp;
+}
+
+static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+        u64 tmp = *prate;
+        u8 frac;
+
+        tmp = tmp * 18 + rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        if (frac < 12)
+                frac = 12;
+        else if (frac > 35)
+                frac = 35;
+        tmp = *prate;
+        tmp *= 18;
+        do_div(tmp, frac);
+
+        return tmp;
+}
+
+static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+        u64 tmp = parent_rate;
+        u8 frac;
+
+        tmp = tmp * 18 + rate / 2;
+        do_div(tmp, rate);
+        frac = tmp;
+        if (frac < 12)
+                frac = 12;
+        else if (frac > 35)
+                frac = 35;
+
+        writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+        writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
+
+        return 0;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+        .enable         = clk_pfd_enable,
+        .disable        = clk_pfd_disable,
+        .recalc_rate    = clk_pfd_recalc_rate,
+        .round_rate     = clk_pfd_round_rate,
+        .set_rate       = clk_pfd_set_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+                        void __iomem *reg, u8 idx)
+{
+        struct clk_pfd *pfd;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+        if (!pfd)
+                return ERR_PTR(-ENOMEM);
+
+        pfd->reg = reg;
+        pfd->idx = idx;
+
+        init.name = name;
+        init.ops = &clk_pfd_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        pfd->hw.init = &init;
+
+        clk = clk_register(NULL, &pfd->hw);
+        if (IS_ERR(clk))
+                kfree(pfd);
+
+        return clk;
+}