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authorShawn Guo <shawn.guo@linaro.org>2012-08-22 09:36:28 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-09-11 07:16:14 -0400
commit0e87e0436c0cc3954eb62181a96d7217ca955a4f (patch)
treed6a376db545f31070ccb6ab8e8c8964052235f5f /arch/arm/mach-imx/clk-imx6q.c
parentfea7a08acb13524b47711625eebea40a0ede69a0 (diff)
ARM: imx6q: replace clk_register_clkdev with clock DT lookup
It really becomes an maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx6q client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c44
1 files changed, 5 insertions, 39 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520b6e22..bbc71f57b92b 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
157}; 157};
158 158
159static struct clk *clk[clk_max]; 159static struct clk *clk[clk_max];
160static struct clk_onecell_data clk_data;
160 161
161static enum mx6q_clks const clks_init_on[] __initconst = { 162static enum mx6q_clks const clks_init_on[] __initconst = {
162 mmdc_ch0_axi, rom, 163 mmdc_ch0_axi, rom,
@@ -392,48 +393,13 @@ int __init mx6q_clocks_init(void)
392 pr_err("i.MX6q clk %d: register failed with %ld\n", 393 pr_err("i.MX6q clk %d: register failed with %ld\n",
393 i, PTR_ERR(clk[i])); 394 i, PTR_ERR(clk[i]));
394 395
396 clk_data.clks = clk;
397 clk_data.clk_num = ARRAY_SIZE(clk);
398 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
399
395 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 400 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
396 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 401 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
397 clk_register_clkdev(clk[twd], NULL, "smp_twd"); 402 clk_register_clkdev(clk[twd], NULL, "smp_twd");
398 clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
399 clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
400 clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
401 clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
402 clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
403 clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
404 clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
405 clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
406 clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
407 clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
408 clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
409 clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
410 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
411 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
412 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
413 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
414 clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
415 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
416 clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
417 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
418 clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
419 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
420 clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
421 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
422 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
423 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
424 clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
425 clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
426 clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
427 clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
428 clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
429 clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
430 clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
431 clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
432 clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
433 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
434 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
435 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
436 clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
437 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 403 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
438 clk_register_clkdev(clk[ahb], "ahb", NULL); 404 clk_register_clkdev(clk[ahb], "ahb", NULL);
439 clk_register_clkdev(clk[cko1], "cko1", NULL); 405 clk_register_clkdev(clk[cko1], "cko1", NULL);