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authorShawn Guo <shawn.guo@freescale.com>2014-05-19 03:43:42 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 04:10:05 -0400
commitc16cc8a0e90e91f250fabf08e2c772e3ce4dca74 (patch)
treea3a4c33cd713d8ebe99d7febcae63cd4ba81ec12 /arch/arm/mach-imx/clk-imx51-imx53.c
parent152e671e91dd3f1b3448040ce6251f0ef95a6ef1 (diff)
ARM: imx5: make mx51_clocks_init() a DT call
Since i.MX51 becomes a DT only platform, we can make mx51_clocks_init() a DT call and save function mx51_clocks_init_dt() now. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx51-imx53.c')
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 21d2b111c83d..1e22d355ad75 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -375,12 +375,10 @@ static void __init mx50_clocks_init(struct device_node *np)
375} 375}
376CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); 376CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
377 377
378int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 378static void __init mx51_clocks_init(struct device_node *np)
379 unsigned long rate_ckih1, unsigned long rate_ckih2)
380{ 379{
381 int i; 380 int i;
382 u32 val; 381 u32 val;
383 struct device_node *np;
384 382
385 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 383 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
386 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); 384 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -422,12 +420,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
422 pr_err("i.MX51 clk %d: register failed with %ld\n", 420 pr_err("i.MX51 clk %d: register failed with %ld\n",
423 i, PTR_ERR(clk[i])); 421 i, PTR_ERR(clk[i]));
424 422
425 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
426 clk_data.clks = clk; 423 clk_data.clks = clk;
427 clk_data.clk_num = ARRAY_SIZE(clk); 424 clk_data.clk_num = ARRAY_SIZE(clk);
428 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 425 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
429 426
430 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); 427 mx5_clocks_common_init(0, 0, 0, 0);
431 428
432 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); 429 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
433 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); 430 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
@@ -474,15 +471,8 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
474 val = readl(MXC_CCM_CLPCR); 471 val = readl(MXC_CCM_CLPCR);
475 val |= 1 << 23; 472 val |= 1 << 23;
476 writel(val, MXC_CCM_CLPCR); 473 writel(val, MXC_CCM_CLPCR);
477
478 return 0;
479}
480
481static void __init mx51_clocks_init_dt(struct device_node *np)
482{
483 mx51_clocks_init(0, 0, 0, 0);
484} 474}
485CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); 475CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
486 476
487static void __init mx53_clocks_init(struct device_node *np) 477static void __init mx53_clocks_init(struct device_node *np)
488{ 478{