Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates from Olof Johansson:
 "This contains the bulk of new SoC development for this merge window.

  Two new platforms have been added, the sunxi platforms (Allwinner A1x
  SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
  series of ARMv7 platforms from them, where the hope is that we can
  keep the platform code generic enough to have them all share one mach
  directory.  The new Broadcom platform is contributed by Christian
  Daudt.

  Highbank has grown support for Calxeda's next generation of hardware,
  ECX-2000.

  clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
  also taken on maintainership of the platform.

  Beyond this there has been a bunch of work from a number of people on
  converting more platforms to IRQ domains, pinctrl conversion, cleanup
  and general feature enablement across most of the active platforms."

Fix up trivial conflicts as per Olof.

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
  mfd: vexpress-sysreg: Remove LEDs code
  irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
  clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
  irq: versatile: delete dangling variable
  ARM: sunxi: add missing include for mdelay()
  ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
  ARM: dts: add node for PL330 MDMA1 controller for exynos4
  ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
  ARM: EXYNOS: add UART3 to DEBUG_LL ports
  ARM: S3C24XX: Add clkdev entry for camif-upll clock
  ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
  ARM: sunxi: Add missing sun4i.dtsi file
  pinctrl: samsung: Do not initialise statics to 0
  ARM i.MX6: remove gate_mask from pllv3
  ARM i.MX6: Fix ethernet PLL clocks
  ARM i.MX6: rename PLLs according to datasheet
  ARM i.MX6: Add pwm support
  ARM i.MX51: Add pwm support
  ARM i.MX53: Add pwm support
  ARM: mx5: Replace clk_register_clkdev with clock DT lookup
  ...

1 files changed, 24 insertions, 20 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index abb71f6b4d60..e8c0473c7568 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -87,6 +87,7 @@ enum imx5_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
                 unsigned long rate_osc, unsigned long rate_ckih1,
@@ -305,6 +306,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_prepare_enable(clk[spba]);
         clk_prepare_enable(clk[emi_fast_gate]); /* fec */
         clk_prepare_enable(clk[emi_slow_gate]); /* eim */
+        clk_prepare_enable(clk[mipi_hsc1_gate]);
+        clk_prepare_enable(clk[mipi_hsc2_gate]);
+        clk_prepare_enable(clk[mipi_esc_gate]);
+        clk_prepare_enable(clk[mipi_hsp_gate]);
         clk_prepare_enable(clk[tmax1]);
         clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
         clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
@@ -314,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
         int i;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -342,16 +348,20 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX51 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
         clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -365,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -392,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 {
         int i;
         unsigned long r;
+        struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -436,15 +443,20 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         pr_err("i.MX53 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
         clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
         clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
+        clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
         clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
@@ -458,14 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
-        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
-        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
-        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
-        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);