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authorSascha Hauer <s.hauer@pengutronix.de>2012-06-05 07:53:32 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2012-11-16 10:33:30 -0500
commit9a2d4825a9368e018003a2732a61be063d178f67 (patch)
tree7a9bedd80689cb45f718b10609b6768e918d0a07 /arch/arm/mach-imx/clk-imx51-imx53.c
parent80be8aa31e97fc2eae4e5856b2e1aa6b2eb1954f (diff)
ARM i.MX5: switch IPU clk support to devicetree bindings
The i.MX5 clk support has platform based clock bindings for the IPU. IPU support is devicetree only, so move them over to devicetree based bindings. Also, enable MIPI clocks which do not have a device associated with, but still need to be enabled to do graphics on i.MX51. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx51-imx53.c')
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c19
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6cb97952bbfb..73b241db63c8 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -305,6 +305,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
305 clk_prepare_enable(clk[spba]); 305 clk_prepare_enable(clk[spba]);
306 clk_prepare_enable(clk[emi_fast_gate]); /* fec */ 306 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
307 clk_prepare_enable(clk[emi_slow_gate]); /* eim */ 307 clk_prepare_enable(clk[emi_slow_gate]); /* eim */
308 clk_prepare_enable(clk[mipi_hsc1_gate]);
309 clk_prepare_enable(clk[mipi_hsc2_gate]);
310 clk_prepare_enable(clk[mipi_esc_gate]);
311 clk_prepare_enable(clk[mipi_hsp_gate]);
308 clk_prepare_enable(clk[tmax1]); 312 clk_prepare_enable(clk[tmax1]);
309 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ 313 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
310 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ 314 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
@@ -348,10 +352,9 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
348 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); 352 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
349 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); 353 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
350 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); 354 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
351 clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu"); 355 clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
352 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu"); 356 clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
353 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu"); 357 clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
354 clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
355 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); 358 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
356 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); 359 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
357 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); 360 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -441,10 +444,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
441 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); 444 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
442 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 445 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
443 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); 446 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
444 clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu"); 447 clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
445 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu"); 448 clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
446 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu"); 449 clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
447 clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu"); 450 clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
448 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); 451 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
449 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); 452 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
450 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); 453 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");