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authorSascha Hauer <s.hauer@pengutronix.de>2012-04-03 06:41:13 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2012-05-09 02:59:34 -0400
commit5b48a6145466f1e2b58b31b1673ec413dabdab2a (patch)
tree61ecab1323d365aeb6482780321399df2e9efd49 /arch/arm/mach-imx/clk-imx35.c
parentb8d4176fa59eff3c21f54125ba3d010a904b9707 (diff)
ARM i.MX35: implement clocks using common clock framework
This patch also adds the SPDIF baud clock mux and dividers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx35.c')
-rw-r--r--arch/arm/mach-imx/clk-imx35.c278
1 files changed, 278 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
new file mode 100644
index 000000000000..a9e60bf7dd75
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -0,0 +1,278 @@
1/*
2 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/err.h>
16
17#include <mach/hardware.h>
18#include <mach/common.h>
19
20#include "crmregs-imx3.h"
21#include "clk.h"
22
23struct arm_ahb_div {
24 unsigned char arm, ahb, sel;
25};
26
27static struct arm_ahb_div clk_consumer[] = {
28 { .arm = 1, .ahb = 4, .sel = 0},
29 { .arm = 1, .ahb = 3, .sel = 1},
30 { .arm = 2, .ahb = 2, .sel = 0},
31 { .arm = 0, .ahb = 0, .sel = 0},
32 { .arm = 0, .ahb = 0, .sel = 0},
33 { .arm = 0, .ahb = 0, .sel = 0},
34 { .arm = 4, .ahb = 1, .sel = 0},
35 { .arm = 1, .ahb = 5, .sel = 0},
36 { .arm = 1, .ahb = 8, .sel = 0},
37 { .arm = 1, .ahb = 6, .sel = 1},
38 { .arm = 2, .ahb = 4, .sel = 0},
39 { .arm = 0, .ahb = 0, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 4, .ahb = 2, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44};
45
46static char hsp_div_532[] = { 4, 8, 3, 0 };
47static char hsp_div_400[] = { 3, 6, 3, 0 };
48
49static const char *std_sel[] = {"ppll", "arm"};
50static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
51
52enum mx35_clks {
53 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
54 arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
55 esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
56 spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
57 ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
58 audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
59 edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
60 esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
61 gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
62 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
63 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
64 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
65 wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
66 clk_max
67};
68
69static struct clk *clk[clk_max];
70
71int __init mx35_clocks_init()
72{
73 void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
74 u32 pdr0, consumer_sel, hsp_sel;
75 struct arm_ahb_div *aad;
76 unsigned char *hsp_div;
77 int i;
78
79 pdr0 = __raw_readl(base + MXC_CCM_PDR0);
80 consumer_sel = (pdr0 >> 16) & 0xf;
81 aad = &clk_consumer[consumer_sel];
82 if (!aad->arm) {
83 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
84 /*
85 * We are basically stuck. Continue with a default entry and hope we
86 * get far enough to actually show the above message
87 */
88 aad = &clk_consumer[0];
89 }
90
91 clk[ckih] = imx_clk_fixed("ckih", 24000000);
92 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
93 clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
94
95 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
96
97 if (aad->sel)
98 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
99 else
100 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
101
102 if (clk_get_rate(clk[arm]) > 400000000)
103 hsp_div = hsp_div_532;
104 else
105 hsp_div = hsp_div_400;
106
107 hsp_sel = (pdr0 >> 20) & 0x3;
108 if (!hsp_div[hsp_sel]) {
109 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
110 hsp_sel = 0;
111 }
112
113 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
114
115 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
116 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
117
118 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
119 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
120 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
121
122 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
123 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
124
125 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
126 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
127 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
128 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
129
130 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
131 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */
132 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
133
134 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
135 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
136 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
137 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
138 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
139
140 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
141 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
142
143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
144
145 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
146 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
147 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
148 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6);
149 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8);
150 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
151 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
152 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
153 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16);
154 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
155 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
156 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
157 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24);
158 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
159 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
160 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
161
162 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0);
163 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2);
164 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4);
165 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6);
166 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8);
167 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
168 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
169 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
170 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
171 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
172 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
173 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
174 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
175 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
176 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
177 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
178
179 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0);
180 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2);
181 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4);
182 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6);
183 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8);
184 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
185 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
186 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
187 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
188 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
189 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
190 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
191 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
192 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
193 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
194
195 clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0);
196 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
197 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
198
199 for (i = 0; i < ARRAY_SIZE(clk); i++)
200 if (IS_ERR(clk[i]))
201 pr_err("i.MX35 clk %d: register failed with %ld\n",
202 i, PTR_ERR(clk[i]));
203
204
205 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
206 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
207 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
208 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
209 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
210 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
211 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
212 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
213 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
214 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
215 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
216 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
217 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
218 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
219 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
220 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
221 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
222 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
223 /* i.mx35 has the i.mx27 type fec */
224 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
225 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
226 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
227 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
228 clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
229 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
230 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
231 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
232 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
233 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
234 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
235 clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
236 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
237 clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
238 /* i.mx35 has the i.mx21 type uart */
239 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
240 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
241 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
242 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
243 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
244 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
245 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
246 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
247 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
248 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
249 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
250 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
251 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
252 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
253 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
254 clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
255 clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
256 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
258 clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
259
260 clk_prepare_enable(clk[spba_gate]);
261 clk_prepare_enable(clk[gpio1_gate]);
262 clk_prepare_enable(clk[gpio2_gate]);
263 clk_prepare_enable(clk[gpio3_gate]);
264 clk_prepare_enable(clk[iim_gate]);
265 clk_prepare_enable(clk[emi_gate]);
266
267 imx_print_silicon_rev("i.MX35", mx35_revision());
268
269#ifdef CONFIG_MXC_USE_EPIT
270 epit_timer_init(&epit1_clk,
271 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
272#else
273 mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
274 MX35_INT_GPT);
275#endif
276
277 return 0;
278}
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