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authorRob Herring <rob.herring@calxeda.com>2012-10-25 13:13:47 -0400
committerRob Herring <rob.herring@calxeda.com>2012-10-31 14:46:50 -0400
commit7a2848d369b2b9281400e6c9f08e21ec71cd1dcb (patch)
treeabb8983696264faee745f49a8132589134f0e791 /arch/arm/mach-highbank/highbank.c
parent0336517b38c5fd643784eeee8f0d73efd48e3361 (diff)
ARM: highbank: abstract out SCU usage
In preparation for A15 support on ECX-2000, the direct calls to SCU registers must be conditional. The SCU power mode register is replaced by a custom register on ECX-2000. Rather than read the number of cores from the SCU, just hardcode it to 4. This removes one use of SCU and removes the need for the SCU to be statically mapped. The cpu initialization will ultimately come from DT. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-highbank/highbank.c')
-rw-r--r--arch/arm/mach-highbank/highbank.c21
1 files changed, 5 insertions, 16 deletions
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 40e36a50304c..3da921a1a7f6 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -28,30 +28,19 @@
28 28
29#include <asm/cacheflush.h> 29#include <asm/cacheflush.h>
30#include <asm/smp_plat.h> 30#include <asm/smp_plat.h>
31#include <asm/smp_scu.h>
32#include <asm/smp_twd.h> 31#include <asm/smp_twd.h>
33#include <asm/hardware/arm_timer.h> 32#include <asm/hardware/arm_timer.h>
34#include <asm/hardware/timer-sp.h> 33#include <asm/hardware/timer-sp.h>
35#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
36#include <asm/hardware/cache-l2x0.h> 35#include <asm/hardware/cache-l2x0.h>
37#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/time.h> 37#include <asm/mach/time.h>
40 38
41#include "core.h" 39#include "core.h"
42#include "sysregs.h" 40#include "sysregs.h"
43 41
44void __iomem *sregs_base; 42void __iomem *sregs_base;
45 43void __iomem *scu_base_addr;
46#define HB_SCU_VIRT_BASE 0xfee00000
47void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
48
49static struct map_desc scu_io_desc __initdata = {
50 .virtual = HB_SCU_VIRT_BASE,
51 .pfn = 0, /* run-time */
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54};
55 44
56static void __init highbank_scu_map_io(void) 45static void __init highbank_scu_map_io(void)
57{ 46{
@@ -60,13 +49,11 @@ static void __init highbank_scu_map_io(void)
60 /* Get SCU base */ 49 /* Get SCU base */
61 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); 50 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
62 51
63 scu_io_desc.pfn = __phys_to_pfn(base); 52 scu_base_addr = ioremap(base, SZ_4K);
64 iotable_init(&scu_io_desc, 1);
65} 53}
66 54
67static void __init highbank_map_io(void) 55static void __init highbank_map_io(void)
68{ 56{
69 highbank_scu_map_io();
70 highbank_lluart_map_io(); 57 highbank_lluart_map_io();
71} 58}
72 59
@@ -99,6 +86,9 @@ static void __init highbank_init_irq(void)
99{ 86{
100 of_irq_init(irq_match); 87 of_irq_init(irq_match);
101 88
89 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
90 highbank_scu_map_io();
91
102#ifdef CONFIG_CACHE_L2X0 92#ifdef CONFIG_CACHE_L2X0
103 /* Enable PL310 L2 Cache controller */ 93 /* Enable PL310 L2 Cache controller */
104 highbank_smc1(0x102, 0x1); 94 highbank_smc1(0x102, 0x1);
@@ -145,7 +135,6 @@ static struct sys_timer highbank_timer = {
145static void highbank_power_off(void) 135static void highbank_power_off(void)
146{ 136{
147 hignbank_set_pwr_shutdown(); 137 hignbank_set_pwr_shutdown();
148 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
149 138
150 while (1) 139 while (1)
151 cpu_do_idle(); 140 cpu_do_idle();