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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-06 13:53:39 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-06 13:59:54 -0400
commit0cd61b68c340a4f901a06e8bb5e0dea4353161c0 (patch)
treecfd72be941ecd172627a06dd61d98b55cec63a39 /arch/arm/mach-h720x
parentda104a83692cf07434ab3b20bf10093bdbc3f97e (diff)
Initial blind fixup for arm for irq changes
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm/mach-h720x')
-rw-r--r--arch/arm/mach-h720x/common.c29
-rw-r--r--arch/arm/mach-h720x/cpu-h7201.c4
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c11
3 files changed, 19 insertions, 25 deletions
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index c096b4569308..4719229a1a78 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -101,14 +101,14 @@ static void inline unmask_gpio_irq(u32 irq)
101 101
102static void 102static void
103h720x_gpio_handler(unsigned int mask, unsigned int irq, 103h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irqdesc *desc, struct pt_regs *regs) 104 struct irqdesc *desc)
105{ 105{
106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq); 106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
107 desc = irq_desc + irq; 107 desc = irq_desc + irq;
108 while (mask) { 108 while (mask) {
109 if (mask & 1) { 109 if (mask & 1) {
110 IRQDBG("handling irq %d\n", irq); 110 IRQDBG("handling irq %d\n", irq);
111 desc_handle_irq(irq, desc, regs); 111 desc_handle_irq(irq, desc);
112 } 112 }
113 irq++; 113 irq++;
114 desc++; 114 desc++;
@@ -117,63 +117,58 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
117} 117}
118 118
119static void 119static void
120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
121 struct pt_regs *regs)
122{ 121{
123 unsigned int mask, irq; 122 unsigned int mask, irq;
124 123
125 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); 124 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
126 irq = IRQ_CHAINED_GPIOA(0); 125 irq = IRQ_CHAINED_GPIOA(0);
127 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 126 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
128 h720x_gpio_handler(mask, irq, desc, regs); 127 h720x_gpio_handler(mask, irq, desc);
129} 128}
130 129
131static void 130static void
132h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
133 struct pt_regs *regs)
134{ 132{
135 unsigned int mask, irq; 133 unsigned int mask, irq;
136 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
137 irq = IRQ_CHAINED_GPIOB(0); 135 irq = IRQ_CHAINED_GPIOB(0);
138 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 136 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
139 h720x_gpio_handler(mask, irq, desc, regs); 137 h720x_gpio_handler(mask, irq, desc);
140} 138}
141 139
142static void 140static void
143h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
144 struct pt_regs *regs)
145{ 142{
146 unsigned int mask, irq; 143 unsigned int mask, irq;
147 144
148 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); 145 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
149 irq = IRQ_CHAINED_GPIOC(0); 146 irq = IRQ_CHAINED_GPIOC(0);
150 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 147 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
151 h720x_gpio_handler(mask, irq, desc, regs); 148 h720x_gpio_handler(mask, irq, desc);
152} 149}
153 150
154static void 151static void
155h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
156 struct pt_regs *regs)
157{ 153{
158 unsigned int mask, irq; 154 unsigned int mask, irq;
159 155
160 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); 156 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
161 irq = IRQ_CHAINED_GPIOD(0); 157 irq = IRQ_CHAINED_GPIOD(0);
162 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 158 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
163 h720x_gpio_handler(mask, irq, desc, regs); 159 h720x_gpio_handler(mask, irq, desc);
164} 160}
165 161
166#ifdef CONFIG_CPU_H7202 162#ifdef CONFIG_CPU_H7202
167static void 163static void
168h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
169 struct pt_regs *regs)
170{ 165{
171 unsigned int mask, irq; 166 unsigned int mask, irq;
172 167
173 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); 168 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
174 irq = IRQ_CHAINED_GPIOE(0); 169 irq = IRQ_CHAINED_GPIOE(0);
175 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 170 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
176 h720x_gpio_handler(mask, irq, desc, regs); 171 h720x_gpio_handler(mask, irq, desc);
177} 172}
178#endif 173#endif
179 174
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
index a9a8255a3a03..13f76bdb3d9d 100644
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ b/arch/arm/mach-h720x/cpu-h7201.c
@@ -27,12 +27,12 @@
27 * Timer interrupt handler 27 * Timer interrupt handler
28 */ 28 */
29static irqreturn_t 29static irqreturn_t
30h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 30h7201_timer_interrupt(int irq, void *dev_id)
31{ 31{
32 write_seqlock(&xtime_lock); 32 write_seqlock(&xtime_lock);
33 33
34 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); 34 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
35 timer_tick(regs); 35 timer_tick();
36 36
37 write_sequnlock(&xtime_lock); 37 write_sequnlock(&xtime_lock);
38 38
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index da678d163fd9..06fecaefd8dc 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -106,8 +106,7 @@ static struct platform_device *devices[] __initdata = {
106 * we have to handle all timer interrupts in one place. 106 * we have to handle all timer interrupts in one place.
107 */ 107 */
108static void 108static void
109h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 109h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
110 struct pt_regs *regs)
111{ 110{
112 unsigned int mask, irq; 111 unsigned int mask, irq;
113 112
@@ -115,7 +114,7 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
115 114
116 if ( mask & TSTAT_T0INT ) { 115 if ( mask & TSTAT_T0INT ) {
117 write_seqlock(&xtime_lock); 116 write_seqlock(&xtime_lock);
118 timer_tick(regs); 117 timer_tick();
119 write_sequnlock(&xtime_lock); 118 write_sequnlock(&xtime_lock);
120 if( mask == TSTAT_T0INT ) 119 if( mask == TSTAT_T0INT )
121 return; 120 return;
@@ -126,7 +125,7 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
126 desc = irq_desc + irq; 125 desc = irq_desc + irq;
127 while (mask) { 126 while (mask) {
128 if (mask & 1) 127 if (mask & 1)
129 desc_handle_irq(irq, desc, regs); 128 desc_handle_irq(irq, desc);
130 irq++; 129 irq++;
131 desc++; 130 desc++;
132 mask >>= 1; 131 mask >>= 1;
@@ -137,9 +136,9 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
137 * Timer interrupt handler 136 * Timer interrupt handler
138 */ 137 */
139static irqreturn_t 138static irqreturn_t
140h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 139h7202_timer_interrupt(int irq, void *dev_id)
141{ 140{
142 h7202_timerx_demux_handler(0, NULL, regs); 141 h7202_timerx_demux_handler(0, NULL);
143 return IRQ_HANDLED; 142 return IRQ_HANDLED;
144} 143}
145 144