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authorArnd Bergmann <arnd@arndb.de>2012-01-09 11:01:00 -0500
committerArnd Bergmann <arnd@arndb.de>2012-01-09 11:01:00 -0500
commita07613a54d700a974f3a4a657da78ef5d097315d (patch)
treee4bc91713e02fa6d8f08b07de53ea8f905593dfa /arch/arm/mach-exynos
parent65db039bf7402f0a5b19cbf6dcff55ebea433b8b (diff)
parent928a11ba36f999436915ea2b1eadf54301f93059 (diff)
Merge branch 'samsung/dt' into samsung/cleanup
Conflicts: arch/arm/mach-s3c64xx/Makefile arch/arm/mach-s5pc100/Makefile arch/arm/mach-s5pv210/Makefile Pull in previously resolved conflicts: The Makefiles were reorganized in the "rmk/restart" series and modified in the "samsung/cleanup series". This also pulls in the other conflict resolutions from the restart series against the samsung/dt series. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-exynos/Makefile9
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c3
-rw-r--r--arch/arm/mach-exynos/clock.c3
-rw-r--r--arch/arm/mach-exynos/common.c698
-rw-r--r--arch/arm/mach-exynos/common.h41
-rw-r--r--arch/arm/mach-exynos/cpu.c313
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S74
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/vmalloc.h22
-rw-r--r--arch/arm/mach-exynos/init.c27
-rw-r--r--arch/arm/mach-exynos/irq-combiner.c124
-rw-r--r--arch/arm/mach-exynos/irq-eint.c237
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c8
-rw-r--r--arch/arm/mach-exynos/mach-origen.c8
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c10
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c10
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c8
-rw-r--r--arch/arm/mach-exynos/platsmp.c28
22 files changed, 795 insertions, 855 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0afcc3b0f870..b4bdf297e9fa 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -17,6 +17,8 @@ choice
17 17
18config ARCH_EXYNOS4 18config ARCH_EXYNOS4
19 bool "SAMSUNG EXYNOS4" 19 bool "SAMSUNG EXYNOS4"
20 select HAVE_SMP
21 select MIGHT_HAVE_CACHE_L2X0
20 help 22 help
21 Samsung EXYNOS4 SoCs based systems 23 Samsung EXYNOS4 SoCs based systems
22 24
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 57e529620804..ca85a99c159d 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,15 +10,17 @@ obj-m :=
10obj-n := 10obj-n :=
11obj- := 11obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o 15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 21
22obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
23
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 24obj-$(CONFIG_SMP) += platsmp.o headsmp.o
23 25
24obj-$(CONFIG_EXYNOS4_MCT) += mct.o 26obj-$(CONFIG_EXYNOS4_MCT) += mct.o
@@ -48,6 +50,7 @@ obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 50obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
49obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
50 52
53obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
51obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 54obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
52obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 55obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
53obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 56obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b9d5ef670eb4..a5823a7f249e 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4210_clock_save[] = { 35static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1), 37 SAVE_ITEM(S5P_CLKSRC_LCD1),
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 77d5decb34fd..26a668b0d101 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4212_clock_save[] = { 35static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5d8d4831e244..5d5250df33fd 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -21,7 +21,6 @@
21#include <plat/pll.h> 21#include <plat/pll.h>
22#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h> 24#include <plat/pm.h>
26 25
27#include <mach/map.h> 26#include <mach/map.h>
@@ -29,6 +28,8 @@
29#include <mach/sysmmu.h> 28#include <mach/sysmmu.h>
30#include <mach/exynos4-clock.h> 29#include <mach/exynos4-clock.h>
31 30
31#include "common.h"
32
32static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
new file mode 100644
index 000000000000..b4beb7e2b5b8
--- /dev/null
+++ b/arch/arm/mach-exynos/common.c
@@ -0,0 +1,698 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/sysdev.h>
17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22
23#include <asm/proc-fns.h>
24#include <asm/exception.h>
25#include <asm/hardware/cache-l2x0.h>
26#include <asm/hardware/gic.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/regs-irq.h>
31#include <mach/regs-pmu.h>
32#include <mach/regs-gpio.h>
33
34#include <plat/cpu.h>
35#include <plat/clock.h>
36#include <plat/devs.h>
37#include <plat/pm.h>
38#include <plat/sdhci.h>
39#include <plat/gpio-cfg.h>
40#include <plat/adc-core.h>
41#include <plat/fb-core.h>
42#include <plat/fimc-core.h>
43#include <plat/iic-core.h>
44#include <plat/tv-core.h>
45#include <plat/regs-serial.h>
46
47#include "common.h"
48
49static const char name_exynos4210[] = "EXYNOS4210";
50static const char name_exynos4212[] = "EXYNOS4212";
51static const char name_exynos4412[] = "EXYNOS4412";
52
53static struct cpu_table cpu_ids[] __initdata = {
54 {
55 .idcode = EXYNOS4210_CPU_ID,
56 .idmask = EXYNOS4_CPU_MASK,
57 .map_io = exynos4_map_io,
58 .init_clocks = exynos4_init_clocks,
59 .init_uarts = exynos4_init_uarts,
60 .init = exynos_init,
61 .name = name_exynos4210,
62 }, {
63 .idcode = EXYNOS4212_CPU_ID,
64 .idmask = EXYNOS4_CPU_MASK,
65 .map_io = exynos4_map_io,
66 .init_clocks = exynos4_init_clocks,
67 .init_uarts = exynos4_init_uarts,
68 .init = exynos_init,
69 .name = name_exynos4212,
70 }, {
71 .idcode = EXYNOS4412_CPU_ID,
72 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts,
76 .init = exynos_init,
77 .name = name_exynos4412,
78 },
79};
80
81/* Initial IO mappings */
82
83static struct map_desc exynos_iodesc[] __initdata = {
84 {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
92 .length = SZ_64K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S5P_VA_SYSTIMER,
111 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)S5P_VA_PMU,
116 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
117 .length = SZ_64K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
121 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
122 .length = SZ_4K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S5P_VA_GIC_CPU,
126 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
127 .length = SZ_64K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S5P_VA_GIC_DIST,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
132 .length = SZ_64K,
133 .type = MT_DEVICE,
134 }, {
135 .virtual = (unsigned long)S3C_VA_UART,
136 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
137 .length = SZ_512K,
138 .type = MT_DEVICE,
139 },
140};
141
142static struct map_desc exynos4_iodesc[] __initdata = {
143 {
144 .virtual = (unsigned long)S5P_VA_CMU,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
146 .length = SZ_128K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
151 .length = SZ_8K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S5P_VA_L2CC,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
156 .length = SZ_4K,
157 .type = MT_DEVICE,
158 }, {
159 .virtual = (unsigned long)S5P_VA_GPIO1,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
161 .length = SZ_4K,
162 .type = MT_DEVICE,
163 }, {
164 .virtual = (unsigned long)S5P_VA_GPIO2,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
166 .length = SZ_4K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S5P_VA_GPIO3,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
171 .length = SZ_256,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S5P_VA_DMC0,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
176 .length = SZ_4K,
177 .type = MT_DEVICE,
178 }, {
179 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
180 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
181 .length = SZ_4K,
182 .type = MT_DEVICE,
183 },
184};
185
186static struct map_desc exynos4_iodesc0[] __initdata = {
187 {
188 .virtual = (unsigned long)S5P_VA_SYSRAM,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
190 .length = SZ_4K,
191 .type = MT_DEVICE,
192 },
193};
194
195static struct map_desc exynos4_iodesc1[] __initdata = {
196 {
197 .virtual = (unsigned long)S5P_VA_SYSRAM,
198 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
199 .length = SZ_4K,
200 .type = MT_DEVICE,
201 },
202};
203
204static void exynos_idle(void)
205{
206 if (!need_resched())
207 cpu_do_idle();
208
209 local_irq_enable();
210}
211
212void exynos4_restart(char mode, const char *cmd)
213{
214 __raw_writel(0x1, S5P_SWRESET);
215}
216
217/*
218 * exynos_map_io
219 *
220 * register the standard cpu IO areas
221 */
222
223void __init exynos_init_io(struct map_desc *mach_desc, int size)
224{
225 /* initialize the io descriptors we need for initialization */
226 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
227 if (mach_desc)
228 iotable_init(mach_desc, size);
229
230 /* detect cpu id and rev. */
231 s5p_init_cpu(S5P_VA_CHIPID);
232
233 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
234}
235
236void __init exynos4_map_io(void)
237{
238 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
239
240 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
241 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
242 else
243 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
244
245 /* initialize device information early */
246 exynos4_default_sdhci0();
247 exynos4_default_sdhci1();
248 exynos4_default_sdhci2();
249 exynos4_default_sdhci3();
250
251 s3c_adc_setname("samsung-adc-v3");
252
253 s3c_fimc_setname(0, "exynos4-fimc");
254 s3c_fimc_setname(1, "exynos4-fimc");
255 s3c_fimc_setname(2, "exynos4-fimc");
256 s3c_fimc_setname(3, "exynos4-fimc");
257
258 /* The I2C bus controllers are directly compatible with s3c2440 */
259 s3c_i2c0_setname("s3c2440-i2c");
260 s3c_i2c1_setname("s3c2440-i2c");
261 s3c_i2c2_setname("s3c2440-i2c");
262
263 s5p_fb_setname(0, "exynos4-fb");
264 s5p_hdmi_setname("exynos4-hdmi");
265}
266
267void __init exynos4_init_clocks(int xtal)
268{
269 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
270
271 s3c24xx_register_baseclocks(xtal);
272 s5p_register_clocks(xtal);
273
274 if (soc_is_exynos4210())
275 exynos4210_register_clocks();
276 else if (soc_is_exynos4212() || soc_is_exynos4412())
277 exynos4212_register_clocks();
278
279 exynos4_register_clocks();
280 exynos4_setup_clocks();
281}
282
283#define COMBINER_ENABLE_SET 0x0
284#define COMBINER_ENABLE_CLEAR 0x4
285#define COMBINER_INT_STATUS 0xC
286
287static DEFINE_SPINLOCK(irq_controller_lock);
288
289struct combiner_chip_data {
290 unsigned int irq_offset;
291 unsigned int irq_mask;
292 void __iomem *base;
293};
294
295static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
296
297static inline void __iomem *combiner_base(struct irq_data *data)
298{
299 struct combiner_chip_data *combiner_data =
300 irq_data_get_irq_chip_data(data);
301
302 return combiner_data->base;
303}
304
305static void combiner_mask_irq(struct irq_data *data)
306{
307 u32 mask = 1 << (data->irq % 32);
308
309 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
310}
311
312static void combiner_unmask_irq(struct irq_data *data)
313{
314 u32 mask = 1 << (data->irq % 32);
315
316 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
317}
318
319static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
320{
321 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
322 struct irq_chip *chip = irq_get_chip(irq);
323 unsigned int cascade_irq, combiner_irq;
324 unsigned long status;
325
326 chained_irq_enter(chip, desc);
327
328 spin_lock(&irq_controller_lock);
329 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
330 spin_unlock(&irq_controller_lock);
331 status &= chip_data->irq_mask;
332
333 if (status == 0)
334 goto out;
335
336 combiner_irq = __ffs(status);
337
338 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
339 if (unlikely(cascade_irq >= NR_IRQS))
340 do_bad_IRQ(cascade_irq, desc);
341 else
342 generic_handle_irq(cascade_irq);
343
344 out:
345 chained_irq_exit(chip, desc);
346}
347
348static struct irq_chip combiner_chip = {
349 .name = "COMBINER",
350 .irq_mask = combiner_mask_irq,
351 .irq_unmask = combiner_unmask_irq,
352};
353
354static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
355{
356 if (combiner_nr >= MAX_COMBINER_NR)
357 BUG();
358 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
359 BUG();
360 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
361}
362
363static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
364 unsigned int irq_start)
365{
366 unsigned int i;
367
368 if (combiner_nr >= MAX_COMBINER_NR)
369 BUG();
370
371 combiner_data[combiner_nr].base = base;
372 combiner_data[combiner_nr].irq_offset = irq_start;
373 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
374
375 /* Disable all interrupts */
376
377 __raw_writel(combiner_data[combiner_nr].irq_mask,
378 base + COMBINER_ENABLE_CLEAR);
379
380 /* Setup the Linux IRQ subsystem */
381
382 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
383 + MAX_IRQ_IN_COMBINER; i++) {
384 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
385 irq_set_chip_data(i, &combiner_data[combiner_nr]);
386 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
387 }
388}
389
390#ifdef CONFIG_OF
391static const struct of_device_id exynos4_dt_irq_match[] = {
392 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
393 {},
394};
395#endif
396
397void __init exynos4_init_irq(void)
398{
399 int irq;
400 unsigned int gic_bank_offset;
401
402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
403
404 if (!of_have_populated_dt())
405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
406#ifdef CONFIG_OF
407 else
408 of_irq_init(exynos4_dt_irq_match);
409#endif
410
411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
412
413 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
414 COMBINER_IRQ(irq, 0));
415 combiner_cascade_irq(irq, IRQ_SPI(irq));
416 }
417
418 /*
419 * The parameters of s5p_init_irq() are for VIC init.
420 * Theses parameters should be NULL and 0 because EXYNOS4
421 * uses GIC instead of VIC.
422 */
423 s5p_init_irq(NULL, 0);
424}
425
426struct sysdev_class exynos4_sysclass = {
427 .name = "exynos4-core",
428};
429
430static struct sys_device exynos4_sysdev = {
431 .cls = &exynos4_sysclass,
432};
433
434static int __init exynos4_core_init(void)
435{
436 return sysdev_class_register(&exynos4_sysclass);
437}
438core_initcall(exynos4_core_init);
439
440#ifdef CONFIG_CACHE_L2X0
441static int __init exynos4_l2x0_cache_init(void)
442{
443 /* TAG, Data Latency Control: 2cycle */
444 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
445
446 if (soc_is_exynos4210())
447 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
448 else if (soc_is_exynos4212() || soc_is_exynos4412())
449 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
450
451 /* L2X0 Prefetch Control */
452 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
453
454 /* L2X0 Power Control */
455 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
456 S5P_VA_L2CC + L2X0_POWER_CTRL);
457
458 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
459
460 return 0;
461}
462
463early_initcall(exynos4_l2x0_cache_init);
464#endif
465
466int __init exynos_init(void)
467{
468 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
469
470 /* set idle function */
471 pm_idle = exynos_idle;
472
473 return sysdev_register(&exynos4_sysdev);
474}
475
476/* uart registration process */
477
478void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
479{
480 struct s3c2410_uartcfg *tcfg = cfg;
481 u32 ucnt;
482
483 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
484 tcfg->has_fracval = 1;
485
486 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
487}
488
489static DEFINE_SPINLOCK(eint_lock);
490
491static unsigned int eint0_15_data[16];
492
493static unsigned int exynos4_get_irq_nr(unsigned int number)
494{
495 u32 ret = 0;
496
497 switch (number) {
498 case 0 ... 3:
499 ret = (number + IRQ_EINT0);
500 break;
501 case 4 ... 7:
502 ret = (number + (IRQ_EINT4 - 4));
503 break;
504 case 8 ... 15:
505 ret = (number + (IRQ_EINT8 - 8));
506 break;
507 default:
508 printk(KERN_ERR "number available : %d\n", number);
509 }
510
511 return ret;
512}
513
514static inline void exynos4_irq_eint_mask(struct irq_data *data)
515{
516 u32 mask;
517
518 spin_lock(&eint_lock);
519 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
520 mask |= eint_irq_to_bit(data->irq);
521 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
522 spin_unlock(&eint_lock);
523}
524
525static void exynos4_irq_eint_unmask(struct irq_data *data)
526{
527 u32 mask;
528
529 spin_lock(&eint_lock);
530 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
531 mask &= ~(eint_irq_to_bit(data->irq));
532 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
533 spin_unlock(&eint_lock);
534}
535
536static inline void exynos4_irq_eint_ack(struct irq_data *data)
537{
538 __raw_writel(eint_irq_to_bit(data->irq),
539 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
540}
541
542static void exynos4_irq_eint_maskack(struct irq_data *data)
543{
544 exynos4_irq_eint_mask(data);
545 exynos4_irq_eint_ack(data);
546}
547
548static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
549{
550 int offs = EINT_OFFSET(data->irq);
551 int shift;
552 u32 ctrl, mask;
553 u32 newvalue = 0;
554
555 switch (type) {
556 case IRQ_TYPE_EDGE_RISING:
557 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
558 break;
559
560 case IRQ_TYPE_EDGE_FALLING:
561 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
562 break;
563
564 case IRQ_TYPE_EDGE_BOTH:
565 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
566 break;
567
568 case IRQ_TYPE_LEVEL_LOW:
569 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
570 break;
571
572 case IRQ_TYPE_LEVEL_HIGH:
573 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
574 break;
575
576 default:
577 printk(KERN_ERR "No such irq type %d", type);
578 return -EINVAL;
579 }
580
581 shift = (offs & 0x7) * 4;
582 mask = 0x7 << shift;
583
584 spin_lock(&eint_lock);
585 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
586 ctrl &= ~mask;
587 ctrl |= newvalue << shift;
588 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
589 spin_unlock(&eint_lock);
590
591 switch (offs) {
592 case 0 ... 7:
593 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
594 break;
595 case 8 ... 15:
596 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
597 break;
598 case 16 ... 23:
599 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
600 break;
601 case 24 ... 31:
602 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
603 break;
604 default:
605 printk(KERN_ERR "No such irq number %d", offs);
606 }
607
608 return 0;
609}
610
611static struct irq_chip exynos4_irq_eint = {
612 .name = "exynos4-eint",
613 .irq_mask = exynos4_irq_eint_mask,
614 .irq_unmask = exynos4_irq_eint_unmask,
615 .irq_mask_ack = exynos4_irq_eint_maskack,
616 .irq_ack = exynos4_irq_eint_ack,
617 .irq_set_type = exynos4_irq_eint_set_type,
618#ifdef CONFIG_PM
619 .irq_set_wake = s3c_irqext_wake,
620#endif
621};
622
623/*
624 * exynos4_irq_demux_eint
625 *
626 * This function demuxes the IRQ from from EINTs 16 to 31.
627 * It is designed to be inlined into the specific handler
628 * s5p_irq_demux_eintX_Y.
629 *
630 * Each EINT pend/mask registers handle eight of them.
631 */
632static inline void exynos4_irq_demux_eint(unsigned int start)
633{
634 unsigned int irq;
635
636 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
637 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
638
639 status &= ~mask;
640 status &= 0xff;
641
642 while (status) {
643 irq = fls(status) - 1;
644 generic_handle_irq(irq + start);
645 status &= ~(1 << irq);
646 }
647}
648
649static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
650{
651 struct irq_chip *chip = irq_get_chip(irq);
652 chained_irq_enter(chip, desc);
653 exynos4_irq_demux_eint(IRQ_EINT(16));
654 exynos4_irq_demux_eint(IRQ_EINT(24));
655 chained_irq_exit(chip, desc);
656}
657
658static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
659{
660 u32 *irq_data = irq_get_handler_data(irq);
661 struct irq_chip *chip = irq_get_chip(irq);
662
663 chained_irq_enter(chip, desc);
664 chip->irq_mask(&desc->irq_data);
665
666 if (chip->irq_ack)
667 chip->irq_ack(&desc->irq_data);
668
669 generic_handle_irq(*irq_data);
670
671 chip->irq_unmask(&desc->irq_data);
672 chained_irq_exit(chip, desc);
673}
674
675int __init exynos4_init_irq_eint(void)
676{
677 int irq;
678
679 for (irq = 0 ; irq <= 31 ; irq++) {
680 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
681 handle_level_irq);
682 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
683 }
684
685 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
686
687 for (irq = 0 ; irq <= 15 ; irq++) {
688 eint0_15_data[irq] = IRQ_EINT(irq);
689
690 irq_set_handler_data(exynos4_get_irq_nr(irq),
691 &eint0_15_data[irq]);
692 irq_set_chained_handler(exynos4_get_irq_nr(irq),
693 exynos4_irq_eint0_15);
694 }
695
696 return 0;
697}
698arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
new file mode 100644
index 000000000000..1ac49de0f398
--- /dev/null
+++ b/arch/arm/mach-exynos/common.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for EXYNOS machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14
15void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void);
17
18void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void);
20
21void exynos4210_register_clocks(void);
22void exynos4212_register_clocks(void);
23
24void exynos4_restart(char mode, const char *cmd);
25
26extern struct sys_timer exynos4_timer;
27
28#ifdef CONFIG_ARCH_EXYNOS
29extern int exynos_init(void);
30extern void exynos4_map_io(void);
31extern void exynos4_init_clocks(int xtal);
32extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
33
34#else
35#define exynos4_init_clocks NULL
36#define exynos4_init_uarts NULL
37#define exynos4_map_io NULL
38#define exynos_init NULL
39#endif
40
41#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
deleted file mode 100644
index 0eb7b6a6903d..000000000000
--- a/arch/arm/mach-exynos/cpu.c
+++ /dev/null
@@ -1,313 +0,0 @@
1/* linux/arch/arm/mach-exynos/cpu.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13#include <linux/of.h>
14#include <linux/of_irq.h>
15
16#include <asm/mach/map.h>
17#include <asm/mach/irq.h>
18
19#include <asm/proc-fns.h>
20#include <asm/hardware/cache-l2x0.h>
21#include <asm/hardware/gic.h>
22
23#include <plat/cpu.h>
24#include <plat/clock.h>
25#include <plat/devs.h>
26#include <plat/exynos4.h>
27#include <plat/adc-core.h>
28#include <plat/sdhci.h>
29#include <plat/fb-core.h>
30#include <plat/fimc-core.h>
31#include <plat/iic-core.h>
32#include <plat/reset.h>
33#include <plat/tv-core.h>
34
35#include <mach/regs-irq.h>
36#include <mach/regs-pmu.h>
37
38unsigned int gic_bank_offset __read_mostly;
39
40extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
41 unsigned int irq_start);
42extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
43
44/* Initial IO mappings */
45static struct map_desc exynos_iodesc[] __initdata = {
46 {
47 .virtual = (unsigned long)S5P_VA_SYSTIMER,
48 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
49 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)S5P_VA_PMU,
53 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
54 .length = SZ_64K,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
58 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
59 .length = SZ_4K,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = (unsigned long)S5P_VA_GIC_CPU,
63 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
64 .length = SZ_64K,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = (unsigned long)S5P_VA_GIC_DIST,
68 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
69 .length = SZ_64K,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = (unsigned long)S3C_VA_UART,
73 .pfn = __phys_to_pfn(S3C_PA_UART),
74 .length = SZ_512K,
75 .type = MT_DEVICE,
76 },
77};
78
79static struct map_desc exynos4_iodesc[] __initdata = {
80 {
81 .virtual = (unsigned long)S5P_VA_CMU,
82 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
83 .length = SZ_128K,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
87 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
88 .length = SZ_8K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)S5P_VA_L2CC,
92 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S5P_VA_GPIO1,
97 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = (unsigned long)S5P_VA_GPIO2,
102 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (unsigned long)S5P_VA_GPIO3,
107 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
108 .length = SZ_256,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (unsigned long)S5P_VA_DMC0,
112 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
113 .length = SZ_4K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)S5P_VA_SROMC,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
118 .length = SZ_4K,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
122 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
123 .length = SZ_4K,
124 .type = MT_DEVICE,
125 },
126};
127
128static struct map_desc exynos4_iodesc0[] __initdata = {
129 {
130 .virtual = (unsigned long)S5P_VA_SYSRAM,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 },
135};
136
137static struct map_desc exynos4_iodesc1[] __initdata = {
138 {
139 .virtual = (unsigned long)S5P_VA_SYSRAM,
140 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
141 .length = SZ_4K,
142 .type = MT_DEVICE,
143 },
144};
145
146static void exynos_idle(void)
147{
148 if (!need_resched())
149 cpu_do_idle();
150
151 local_irq_enable();
152}
153
154static void exynos4_sw_reset(void)
155{
156 __raw_writel(0x1, S5P_SWRESET);
157}
158
159/*
160 * exynos_map_io
161 *
162 * register the standard cpu IO areas
163 */
164void __init exynos4_map_io(void)
165{
166 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
167 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
168
169 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
170 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
171 else
172 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
173
174 /* initialize device information early */
175 exynos4_default_sdhci0();
176 exynos4_default_sdhci1();
177 exynos4_default_sdhci2();
178 exynos4_default_sdhci3();
179
180 s3c_adc_setname("samsung-adc-v3");
181
182 s3c_fimc_setname(0, "exynos4-fimc");
183 s3c_fimc_setname(1, "exynos4-fimc");
184 s3c_fimc_setname(2, "exynos4-fimc");
185 s3c_fimc_setname(3, "exynos4-fimc");
186
187 /* The I2C bus controllers are directly compatible with s3c2440 */
188 s3c_i2c0_setname("s3c2440-i2c");
189 s3c_i2c1_setname("s3c2440-i2c");
190 s3c_i2c2_setname("s3c2440-i2c");
191
192 s5p_fb_setname(0, "exynos4-fb");
193 s5p_hdmi_setname("exynos4-hdmi");
194}
195
196void __init exynos4_init_clocks(int xtal)
197{
198 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
199
200 s3c24xx_register_baseclocks(xtal);
201 s5p_register_clocks(xtal);
202
203 if (soc_is_exynos4210())
204 exynos4210_register_clocks();
205 else if (soc_is_exynos4212() || soc_is_exynos4412())
206 exynos4212_register_clocks();
207
208 exynos4_register_clocks();
209 exynos4_setup_clocks();
210}
211
212static void exynos4_gic_irq_fix_base(struct irq_data *d)
213{
214 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
215
216 gic_data->cpu_base = S5P_VA_GIC_CPU +
217 (gic_bank_offset * smp_processor_id());
218
219 gic_data->dist_base = S5P_VA_GIC_DIST +
220 (gic_bank_offset * smp_processor_id());
221}
222
223#ifdef CONFIG_OF
224static const struct of_device_id exynos4_dt_irq_match[] = {
225 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
226 {},
227};
228#endif
229
230void __init exynos4_init_irq(void)
231{
232 int irq;
233
234 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
235
236 if (!of_have_populated_dt())
237 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
238#ifdef CONFIG_OF
239 else
240 of_irq_init(exynos4_dt_irq_match);
241#endif
242
243 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
244 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
245 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
246
247 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
248
249 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
250 COMBINER_IRQ(irq, 0));
251 combiner_cascade_irq(irq, IRQ_SPI(irq));
252 }
253
254 /* The parameters of s5p_init_irq() are for VIC init.
255 * Theses parameters should be NULL and 0 because EXYNOS4
256 * uses GIC instead of VIC.
257 */
258 s5p_init_irq(NULL, 0);
259}
260
261struct sysdev_class exynos4_sysclass = {
262 .name = "exynos4-core",
263};
264
265static struct sys_device exynos4_sysdev = {
266 .cls = &exynos4_sysclass,
267};
268
269static int __init exynos4_core_init(void)
270{
271 return sysdev_class_register(&exynos4_sysclass);
272}
273core_initcall(exynos4_core_init);
274
275#ifdef CONFIG_CACHE_L2X0
276static int __init exynos4_l2x0_cache_init(void)
277{
278 /* TAG, Data Latency Control: 2cycle */
279 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
280
281 if (soc_is_exynos4210())
282 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
283 else if (soc_is_exynos4212() || soc_is_exynos4412())
284 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
285
286 /* L2X0 Prefetch Control */
287 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
288
289 /* L2X0 Power Control */
290 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
291 S5P_VA_L2CC + L2X0_POWER_CTRL);
292
293 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
294
295 return 0;
296}
297
298early_initcall(exynos4_l2x0_cache_init);
299#endif
300
301int __init exynos_init(void)
302{
303 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
304
305 /* set idle function */
306 pm_idle = exynos_idle;
307
308 /* set sw_reset function */
309 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
310 s5p_reset_hook = exynos4_sw_reset;
311
312 return sysdev_register(&exynos4_sysdev);
313}
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index d7dfcd7eb921..3ba4f547534b 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,82 +9,8 @@
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10*/ 10*/
11 11
12#include <mach/hardware.h>
13#include <mach/map.h>
14#include <asm/hardware/gic.h>
15
16 .macro disable_fiq 12 .macro disable_fiq
17 .endm 13 .endm
18 14
19 .macro get_irqnr_preamble, base, tmp
20 mov \tmp, #0
21
22 mrc p15, 0, \base, c0, c0, 5
23 and \base, \base, #3
24 cmp \base, #0
25 beq 1f
26
27 ldr \tmp, =gic_bank_offset
28 ldr \tmp, [\tmp]
29 cmp \base, #1
30 beq 1f
31
32 cmp \base, #2
33 addeq \tmp, \tmp, \tmp
34 addne \tmp, \tmp, \tmp, LSL #1
35
361: ldr \base, =gic_cpu_base_addr
37 ldr \base, [\base]
38 add \base, \base, \tmp
39 .endm
40
41 .macro arch_ret_to_user, tmp1, tmp2 15 .macro arch_ret_to_user, tmp1, tmp2
42 .endm 16 .endm
43
44 /*
45 * The interrupt numbering scheme is defined in the
46 * interrupt controller spec. To wit:
47 *
48 * Interrupts 0-15 are IPI
49 * 16-28 are reserved
50 * 29-31 are local. We allow 30 to be used for the watchdog.
51 * 32-1020 are global
52 * 1021-1022 are reserved
53 * 1023 is "spurious" (no interrupt)
54 *
55 * For now, we ignore all local interrupts so only return an interrupt if it's
56 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
57 *
58 * A simple read from the controller will tell us the number of the highest
59 * priority enabled interrupt. We then just need to check whether it is in the
60 * valid range for an IRQ (30-1020 inclusive).
61 */
62
63 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
64
65 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
66
67 ldr \tmp, =1021
68
69 bic \irqnr, \irqstat, #0x1c00
70
71 cmp \irqnr, #15
72 cmpcc \irqnr, \irqnr
73 cmpne \irqnr, \tmp
74 cmpcs \irqnr, \irqnr
75
76 .endm
77
78 /* We assume that irqstat (the raw value of the IRQ acknowledge
79 * register) is preserved from the macro above.
80 * If there is an IPI, we immediately signal end of interrupt on the
81 * controller, since this requires the original irqstat value which
82 * we won't easily be able to recreate later.
83 */
84
85 .macro test_for_ipi, irqnr, irqstat, base, tmp
86 bic \irqnr, \irqstat, #0x1c00
87 cmp \irqnr, #16
88 strcc \irqstat, [\base, #GIC_CPU_EOI]
89 cmpcs \irqnr, \irqnr
90 .endm
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af0..d1829860a0ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -149,7 +149,6 @@
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 150#define S3C_PA_UART EXYNOS4_PA_UART
151 151
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI 152#define S5P_PA_EHCI EXYNOS4_PA_EHCI
154#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 153#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
155#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 154#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
@@ -166,26 +165,17 @@
166#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 165#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
167#define S5P_PA_SDO EXYNOS4_PA_SDO 166#define S5P_PA_SDO EXYNOS4_PA_SDO
168#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 167#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
169#define S5P_PA_SROMC EXYNOS4_PA_SROMC
170#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
171#define S5P_PA_TIMER EXYNOS4_PA_TIMER
172#define S5P_PA_VP EXYNOS4_PA_VP 168#define S5P_PA_VP EXYNOS4_PA_VP
173 169
174#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 170#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
175#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 171#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
176#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 172#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
177 173
178#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
179#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
180#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
181#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
182#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
183
184/* Compatibility UART */ 174/* Compatibility UART */
185 175
186#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 176#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
187 177
188#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 178#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
189#define S5P_PA_UART0 S5P_PA_UART(0) 179#define S5P_PA_UART0 S5P_PA_UART(0)
190#define S5P_PA_UART1 S5P_PA_UART(1) 180#define S5P_PA_UART1 S5P_PA_UART(1)
191#define S5P_PA_UART2 S5P_PA_UART(2) 181#define S5P_PA_UART2 S5P_PA_UART(2)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 5e3220c18fc7..0063a6de3dc8 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -13,8 +13,6 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16#include <plat/system-reset.h>
17
18static void arch_idle(void) 16static void arch_idle(void)
19{ 17{
20 /* nothing here yet */ 18 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
deleted file mode 100644
index 284330e571d2..000000000000
--- a/arch/arm/mach-exynos/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * EXYNOS4 vmalloc definition
15*/
16
17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__
19
20#define VMALLOC_END 0xF6000000UL
21
22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
deleted file mode 100644
index 5b35978029be..000000000000
--- a/arch/arm/mach-exynos/init.c
+++ /dev/null
@@ -1,27 +0,0 @@
1/* linux/arch/arm/mach-exynos4/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17/* uart registration process */
18void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
19{
20 struct s3c2410_uartcfg *tcfg = cfg;
21 u32 ucnt;
22
23 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
24 tcfg->has_fracval = 1;
25
26 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
27}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
deleted file mode 100644
index 5a2758ab055e..000000000000
--- a/arch/arm/mach-exynos/irq-combiner.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 unsigned int irq_mask;
28 void __iomem *base;
29};
30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32
33static inline void __iomem *combiner_base(struct irq_data *data)
34{
35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
38 return combiner_data->base;
39}
40
41static void combiner_mask_irq(struct irq_data *data)
42{
43 u32 mask = 1 << (data->irq % 32);
44
45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
46}
47
48static void combiner_unmask_irq(struct irq_data *data)
49{
50 u32 mask = 1 << (data->irq % 32);
51
52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
53}
54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{
57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status;
61
62 chained_irq_enter(chip, desc);
63
64 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock);
67 status &= chip_data->irq_mask;
68
69 if (status == 0)
70 goto out;
71
72 combiner_irq = __ffs(status);
73
74 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
75 if (unlikely(cascade_irq >= NR_IRQS))
76 do_bad_IRQ(cascade_irq, desc);
77 else
78 generic_handle_irq(cascade_irq);
79
80 out:
81 chained_irq_exit(chip, desc);
82}
83
84static struct irq_chip combiner_chip = {
85 .name = "COMBINER",
86 .irq_mask = combiner_mask_irq,
87 .irq_unmask = combiner_unmask_irq,
88};
89
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
91{
92 if (combiner_nr >= MAX_COMBINER_NR)
93 BUG();
94 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
95 BUG();
96 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
97}
98
99void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
100 unsigned int irq_start)
101{
102 unsigned int i;
103
104 if (combiner_nr >= MAX_COMBINER_NR)
105 BUG();
106
107 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start;
109 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
110
111 /* Disable all interrupts */
112
113 __raw_writel(combiner_data[combiner_nr].irq_mask,
114 base + COMBINER_ENABLE_CLEAR);
115
116 /* Setup the Linux IRQ subsystem */
117
118 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
119 + MAX_IRQ_IN_COMBINER; i++) {
120 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
121 irq_set_chip_data(i, &combiner_data[combiner_nr]);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 }
124}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
deleted file mode 100644
index badb8c66fc9b..000000000000
--- a/arch/arm/mach-exynos/irq-eint.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26#include <asm/mach/irq.h>
27
28static DEFINE_SPINLOCK(eint_lock);
29
30static unsigned int eint0_15_data[16];
31
32static unsigned int exynos4_get_irq_nr(unsigned int number)
33{
34 u32 ret = 0;
35
36 switch (number) {
37 case 0 ... 3:
38 ret = (number + IRQ_EINT0);
39 break;
40 case 4 ... 7:
41 ret = (number + (IRQ_EINT4 - 4));
42 break;
43 case 8 ... 15:
44 ret = (number + (IRQ_EINT8 - 8));
45 break;
46 default:
47 printk(KERN_ERR "number available : %d\n", number);
48 }
49
50 return ret;
51}
52
53static inline void exynos4_irq_eint_mask(struct irq_data *data)
54{
55 u32 mask;
56
57 spin_lock(&eint_lock);
58 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 mask |= eint_irq_to_bit(data->irq);
60 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
61 spin_unlock(&eint_lock);
62}
63
64static void exynos4_irq_eint_unmask(struct irq_data *data)
65{
66 u32 mask;
67
68 spin_lock(&eint_lock);
69 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 mask &= ~(eint_irq_to_bit(data->irq));
71 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
72 spin_unlock(&eint_lock);
73}
74
75static inline void exynos4_irq_eint_ack(struct irq_data *data)
76{
77 __raw_writel(eint_irq_to_bit(data->irq),
78 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
79}
80
81static void exynos4_irq_eint_maskack(struct irq_data *data)
82{
83 exynos4_irq_eint_mask(data);
84 exynos4_irq_eint_ack(data);
85}
86
87static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
88{
89 int offs = EINT_OFFSET(data->irq);
90 int shift;
91 u32 ctrl, mask;
92 u32 newvalue = 0;
93
94 switch (type) {
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -EINVAL;
118 }
119
120 shift = (offs & 0x7) * 4;
121 mask = 0x7 << shift;
122
123 spin_lock(&eint_lock);
124 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 ctrl &= ~mask;
126 ctrl |= newvalue << shift;
127 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
128 spin_unlock(&eint_lock);
129
130 switch (offs) {
131 case 0 ... 7:
132 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
133 break;
134 case 8 ... 15:
135 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
136 break;
137 case 16 ... 23:
138 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
139 break;
140 case 24 ... 31:
141 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
142 break;
143 default:
144 printk(KERN_ERR "No such irq number %d", offs);
145 }
146
147 return 0;
148}
149
150static struct irq_chip exynos4_irq_eint = {
151 .name = "exynos4-eint",
152 .irq_mask = exynos4_irq_eint_mask,
153 .irq_unmask = exynos4_irq_eint_unmask,
154 .irq_mask_ack = exynos4_irq_eint_maskack,
155 .irq_ack = exynos4_irq_eint_ack,
156 .irq_set_type = exynos4_irq_eint_set_type,
157#ifdef CONFIG_PM
158 .irq_set_wake = s3c_irqext_wake,
159#endif
160};
161
162/* exynos4_irq_demux_eint
163 *
164 * This function demuxes the IRQ from from EINTs 16 to 31.
165 * It is designed to be inlined into the specific handler
166 * s5p_irq_demux_eintX_Y.
167 *
168 * Each EINT pend/mask registers handle eight of them.
169 */
170static inline void exynos4_irq_demux_eint(unsigned int start)
171{
172 unsigned int irq;
173
174 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
175 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
176
177 status &= ~mask;
178 status &= 0xff;
179
180 while (status) {
181 irq = fls(status) - 1;
182 generic_handle_irq(irq + start);
183 status &= ~(1 << irq);
184 }
185}
186
187static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
188{
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
191 exynos4_irq_demux_eint(IRQ_EINT(16));
192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
194}
195
196static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
197{
198 u32 *irq_data = irq_get_handler_data(irq);
199 struct irq_chip *chip = irq_get_chip(irq);
200
201 chained_irq_enter(chip, desc);
202 chip->irq_mask(&desc->irq_data);
203
204 if (chip->irq_ack)
205 chip->irq_ack(&desc->irq_data);
206
207 generic_handle_irq(*irq_data);
208
209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
211}
212
213int __init exynos4_init_irq_eint(void)
214{
215 int irq;
216
217 for (irq = 0 ; irq <= 31 ; irq++) {
218 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
219 handle_level_irq);
220 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
221 }
222
223 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
224
225 for (irq = 0 ; irq <= 15 ; irq++) {
226 eint0_15_data[irq] = IRQ_EINT(irq);
227
228 irq_set_handler_data(exynos4_get_irq_nr(irq),
229 &eint0_15_data[irq]);
230 irq_set_chained_handler(exynos4_get_irq_nr(irq),
231 exynos4_irq_eint0_15);
232 }
233
234 return 0;
235}
236
237arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index f0ca6c157d29..d726fcd3acf9 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -16,11 +16,11 @@
16#include <linux/smsc911x.h> 16#include <linux/smsc911x.h>
17 17
18#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
19#include <asm/hardware/gic.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/cpu.h> 22#include <plat/cpu.h>
22#include <plat/devs.h> 23#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
26#include <plat/regs-srom.h> 26#include <plat/regs-srom.h>
@@ -28,6 +28,8 @@
28 28
29#include <mach/map.h> 29#include <mach/map.h>
30 30
31#include "common.h"
32
31/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \ 35 S3C2410_UCON_RXILEVEL | \
@@ -187,7 +189,7 @@ static void __init armlex4210_smsc911x_init(void)
187 189
188static void __init armlex4210_map_io(void) 190static void __init armlex4210_map_io(void)
189{ 191{
190 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 192 exynos_init_io(NULL, 0);
191 s3c24xx_init_clocks(24000000); 193 s3c24xx_init_clocks(24000000);
192 s3c24xx_init_uarts(armlex4210_uartcfgs, 194 s3c24xx_init_uarts(armlex4210_uartcfgs,
193 ARRAY_SIZE(armlex4210_uartcfgs)); 195 ARRAY_SIZE(armlex4210_uartcfgs));
@@ -210,6 +212,8 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
210 .atag_offset = 0x100, 212 .atag_offset = 0x100,
211 .init_irq = exynos4_init_irq, 213 .init_irq = exynos4_init_irq,
212 .map_io = armlex4210_map_io, 214 .map_io = armlex4210_map_io,
215 .handle_irq = gic_handle_irq,
213 .init_machine = armlex4210_machine_init, 216 .init_machine = armlex4210_machine_init,
214 .timer = &exynos4_timer, 217 .timer = &exynos4_timer,
218 .restart = exynos4_restart,
215MACHINE_END 219MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 205dfed41210..b895ec031105 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -32,12 +32,12 @@
32#include <media/v4l2-mediabus.h> 32#include <media/v4l2-mediabus.h>
33 33
34#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
35#include <asm/hardware/gic.h>
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
36 37
37#include <plat/adc.h> 38#include <plat/adc.h>
38#include <plat/regs-fb-v4.h> 39#include <plat/regs-fb-v4.h>
39#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
40#include <plat/exynos4.h>
41#include <plat/cpu.h> 41#include <plat/cpu.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/fb.h> 43#include <plat/fb.h>
@@ -54,6 +54,8 @@
54 54
55#include <mach/map.h> 55#include <mach/map.h>
56 56
57#include "common.h"
58
57/* Following are default values for UCON, ULCON and UFCON UART registers */ 59/* Following are default values for UCON, ULCON and UFCON UART registers */
58#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 60#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
59 S3C2410_UCON_RXILEVEL | \ 61 S3C2410_UCON_RXILEVEL | \
@@ -1278,7 +1280,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1278 1280
1279static void __init nuri_map_io(void) 1281static void __init nuri_map_io(void)
1280{ 1282{
1281 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 1283 exynos_init_io(NULL, 0);
1282 s3c24xx_init_clocks(24000000); 1284 s3c24xx_init_clocks(24000000);
1283 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1285 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1284} 1286}
@@ -1328,7 +1330,9 @@ MACHINE_START(NURI, "NURI")
1328 .atag_offset = 0x100, 1330 .atag_offset = 0x100,
1329 .init_irq = exynos4_init_irq, 1331 .init_irq = exynos4_init_irq,
1330 .map_io = nuri_map_io, 1332 .map_io = nuri_map_io,
1333 .handle_irq = gic_handle_irq,
1331 .init_machine = nuri_machine_init, 1334 .init_machine = nuri_machine_init,
1332 .timer = &exynos4_timer, 1335 .timer = &exynos4_timer,
1333 .reserve = &nuri_reserve, 1336 .reserve = &nuri_reserve,
1337 .restart = exynos4_restart,
1334MACHINE_END 1338MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f80b563f2be7..586eb995aa96 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -22,13 +22,13 @@
22#include <linux/lcd.h> 22#include <linux/lcd.h>
23 23
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/hardware/gic.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26 27
27#include <video/platform_lcd.h> 28#include <video/platform_lcd.h>
28 29
29#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
30#include <plat/regs-fb-v4.h> 31#include <plat/regs-fb-v4.h>
31#include <plat/exynos4.h>
32#include <plat/cpu.h> 32#include <plat/cpu.h>
33#include <plat/devs.h> 33#include <plat/devs.h>
34#include <plat/sdhci.h> 34#include <plat/sdhci.h>
@@ -43,6 +43,8 @@
43 43
44#include <mach/map.h> 44#include <mach/map.h>
45 45
46#include "common.h"
47
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -638,7 +640,7 @@ static void s5p_tv_setup(void)
638 640
639static void __init origen_map_io(void) 641static void __init origen_map_io(void)
640{ 642{
641 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 643 exynos_init_io(NULL, 0);
642 s3c24xx_init_clocks(24000000); 644 s3c24xx_init_clocks(24000000);
643 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 645 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
644} 646}
@@ -694,7 +696,9 @@ MACHINE_START(ORIGEN, "ORIGEN")
694 .atag_offset = 0x100, 696 .atag_offset = 0x100,
695 .init_irq = exynos4_init_irq, 697 .init_irq = exynos4_init_irq,
696 .map_io = origen_map_io, 698 .map_io = origen_map_io,
699 .handle_irq = gic_handle_irq,
697 .init_machine = origen_machine_init, 700 .init_machine = origen_machine_init,
698 .timer = &exynos4_timer, 701 .timer = &exynos4_timer,
699 .reserve = &origen_reserve, 702 .reserve = &origen_reserve,
703 .restart = exynos4_restart,
700MACHINE_END 704MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fcf2e0e23d53..d00e4f016a68 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -21,13 +21,13 @@
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22 22
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/hardware/gic.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25 26
26#include <plat/backlight.h> 27#include <plat/backlight.h>
27#include <plat/clock.h> 28#include <plat/clock.h>
28#include <plat/cpu.h> 29#include <plat/cpu.h>
29#include <plat/devs.h> 30#include <plat/devs.h>
30#include <plat/exynos4.h>
31#include <plat/gpio-cfg.h> 31#include <plat/gpio-cfg.h>
32#include <plat/iic.h> 32#include <plat/iic.h>
33#include <plat/keypad.h> 33#include <plat/keypad.h>
@@ -36,6 +36,8 @@
36 36
37#include <mach/map.h> 37#include <mach/map.h>
38 38
39#include "common.h"
40
39/* Following are default values for UCON, ULCON and UFCON UART registers */ 41/* Following are default values for UCON, ULCON and UFCON UART registers */
40#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 42#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
41 S3C2410_UCON_RXILEVEL | \ 43 S3C2410_UCON_RXILEVEL | \
@@ -249,7 +251,7 @@ static void __init smdk4x12_map_io(void)
249{ 251{
250 clk_xusbxti.rate = 24000000; 252 clk_xusbxti.rate = 24000000;
251 253
252 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 254 exynos_init_io(NULL, 0);
253 s3c24xx_init_clocks(clk_xusbxti.rate); 255 s3c24xx_init_clocks(clk_xusbxti.rate);
254 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 256 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
255} 257}
@@ -287,8 +289,10 @@ MACHINE_START(SMDK4212, "SMDK4212")
287 .atag_offset = 0x100, 289 .atag_offset = 0x100,
288 .init_irq = exynos4_init_irq, 290 .init_irq = exynos4_init_irq,
289 .map_io = smdk4x12_map_io, 291 .map_io = smdk4x12_map_io,
292 .handle_irq = gic_handle_irq,
290 .init_machine = smdk4x12_machine_init, 293 .init_machine = smdk4x12_machine_init,
291 .timer = &exynos4_timer, 294 .timer = &exynos4_timer,
295 .restart = exynos4_restart,
292MACHINE_END 296MACHINE_END
293 297
294MACHINE_START(SMDK4412, "SMDK4412") 298MACHINE_START(SMDK4412, "SMDK4412")
@@ -297,6 +301,8 @@ MACHINE_START(SMDK4412, "SMDK4412")
297 .atag_offset = 0x100, 301 .atag_offset = 0x100,
298 .init_irq = exynos4_init_irq, 302 .init_irq = exynos4_init_irq,
299 .map_io = smdk4x12_map_io, 303 .map_io = smdk4x12_map_io,
304 .handle_irq = gic_handle_irq,
300 .init_machine = smdk4x12_machine_init, 305 .init_machine = smdk4x12_machine_init,
301 .timer = &exynos4_timer, 306 .timer = &exynos4_timer,
307 .restart = exynos4_restart,
302MACHINE_END 308MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index cbf31bd0e2c9..a27b23eee9fa 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -21,13 +21,13 @@
21#include <linux/pwm_backlight.h> 21#include <linux/pwm_backlight.h>
22 22
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/hardware/gic.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25 26
26#include <video/platform_lcd.h> 27#include <video/platform_lcd.h>
27#include <plat/regs-serial.h> 28#include <plat/regs-serial.h>
28#include <plat/regs-srom.h> 29#include <plat/regs-srom.h>
29#include <plat/regs-fb-v4.h> 30#include <plat/regs-fb-v4.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/fb.h> 33#include <plat/fb.h>
@@ -43,6 +43,8 @@
43 43
44#include <mach/map.h> 44#include <mach/map.h>
45 45
46#include "common.h"
47
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -330,7 +332,7 @@ static void s5p_tv_setup(void)
330 332
331static void __init smdkv310_map_io(void) 333static void __init smdkv310_map_io(void)
332{ 334{
333 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 335 exynos_init_io(NULL, 0);
334 s3c24xx_init_clocks(24000000); 336 s3c24xx_init_clocks(24000000);
335 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 337 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
336} 338}
@@ -373,9 +375,11 @@ MACHINE_START(SMDKV310, "SMDKV310")
373 .atag_offset = 0x100, 375 .atag_offset = 0x100,
374 .init_irq = exynos4_init_irq, 376 .init_irq = exynos4_init_irq,
375 .map_io = smdkv310_map_io, 377 .map_io = smdkv310_map_io,
378 .handle_irq = gic_handle_irq,
376 .init_machine = smdkv310_machine_init, 379 .init_machine = smdkv310_machine_init,
377 .timer = &exynos4_timer, 380 .timer = &exynos4_timer,
378 .reserve = &smdkv310_reserve, 381 .reserve = &smdkv310_reserve,
382 .restart = exynos4_restart,
379MACHINE_END 383MACHINE_END
380 384
381MACHINE_START(SMDKC210, "SMDKC210") 385MACHINE_START(SMDKC210, "SMDKC210")
@@ -383,6 +387,8 @@ MACHINE_START(SMDKC210, "SMDKC210")
383 .atag_offset = 0x100, 387 .atag_offset = 0x100,
384 .init_irq = exynos4_init_irq, 388 .init_irq = exynos4_init_irq,
385 .map_io = smdkv310_map_io, 389 .map_io = smdkv310_map_io,
390 .handle_irq = gic_handle_irq,
386 .init_machine = smdkv310_machine_init, 391 .init_machine = smdkv310_machine_init,
387 .timer = &exynos4_timer, 392 .timer = &exynos4_timer,
393 .restart = exynos4_restart,
388MACHINE_END 394MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 0a04cd643b07..37ac93e8d6d9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -24,10 +24,10 @@
24#include <linux/i2c/atmel_mxt_ts.h> 24#include <linux/i2c/atmel_mxt_ts.h>
25 25
26#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
27#include <asm/hardware/gic.h>
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
28 29
29#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
30#include <plat/exynos4.h>
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/iic.h> 33#include <plat/iic.h>
@@ -47,6 +47,8 @@
47#include <media/s5p_fimc.h> 47#include <media/s5p_fimc.h>
48#include <media/m5mols.h> 48#include <media/m5mols.h>
49 49
50#include "common.h"
51
50/* Following are default values for UCON, ULCON and UFCON UART registers */ 52/* Following are default values for UCON, ULCON and UFCON UART registers */
51#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \ 54 S3C2410_UCON_RXILEVEL | \
@@ -990,7 +992,7 @@ static struct platform_device *universal_devices[] __initdata = {
990 992
991static void __init universal_map_io(void) 993static void __init universal_map_io(void)
992{ 994{
993 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 995 exynos_init_io(NULL, 0);
994 s3c24xx_init_clocks(24000000); 996 s3c24xx_init_clocks(24000000);
995 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
996} 998}
@@ -1054,7 +1056,9 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1054 .atag_offset = 0x100, 1056 .atag_offset = 0x100,
1055 .init_irq = exynos4_init_irq, 1057 .init_irq = exynos4_init_irq,
1056 .map_io = universal_map_io, 1058 .map_io = universal_map_io,
1059 .handle_irq = gic_handle_irq,
1057 .init_machine = universal_machine_init, 1060 .init_machine = universal_machine_init,
1058 .timer = &exynos4_timer, 1061 .timer = &exynos4_timer,
1059 .reserve = &universal_reserve, 1062 .reserve = &universal_reserve,
1063 .restart = exynos4_restart,
1060MACHINE_END 1064MACHINE_END
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb3875..60bc45e3e709 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,6 @@
32 32
33#include <plat/cpu.h> 33#include <plat/cpu.h>
34 34
35extern unsigned int gic_bank_offset;
36extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
37 36
38#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void)
65 64
66static DEFINE_SPINLOCK(boot_lock); 65static DEFINE_SPINLOCK(boot_lock);
67 66
68static void __cpuinit exynos4_gic_secondary_init(void)
69{
70 void __iomem *dist_base = S5P_VA_GIC_DIST +
71 (gic_bank_offset * smp_processor_id());
72 void __iomem *cpu_base = S5P_VA_GIC_CPU +
73 (gic_bank_offset * smp_processor_id());
74 int i;
75
76 /*
77 * Deal with the banked PPI and SGI interrupts - disable all
78 * PPI interrupts, ensure all SGI interrupts are enabled.
79 */
80 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
81 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
82
83 /*
84 * Set priority on PPI and SGI interrupts
85 */
86 for (i = 0; i < 32; i += 4)
87 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
88
89 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
90 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
91}
92
93void __cpuinit platform_secondary_init(unsigned int cpu) 67void __cpuinit platform_secondary_init(unsigned int cpu)
94{ 68{
95 /* 69 /*
@@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
97 * core (e.g. timer irq), then they will not have been enabled 71 * core (e.g. timer irq), then they will not have been enabled
98 * for us: do so 72 * for us: do so
99 */ 73 */
100 exynos4_gic_secondary_init(); 74 gic_secondary_init(0);
101 75
102 /* 76 /*
103 * let the primary processor know we're out of the 77 * let the primary processor know we're out of the
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 23:12:45 -0500