ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

2 files changed, 46 insertions, 2 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 84ef35aceba2..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+        .clk    = {
+                .name           = "mout_bpll_fout",
+        },
+        .sources = &clk_src_bpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+        [0] = &clk_fin_bpll,
+        [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+        .sources        = exynos5_clk_src_bpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
         .clk    = {
                 .name           = "mout_bpll",
         },
-        .sources = &clk_src_bpll,
+        .sources = &exynos5_clk_src_bpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 };
 
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+        .clk    = {
+                .name           = "mout_mpll_fout",
+        },
+        .sources = &clk_src_mpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+        .sources        = exynos5_clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
-        .sources = &clk_src_mpll,
+        .sources = &exynos5_clk_src_mpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -1036,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mout_apll,
         &exynos5_clk_sclk_apll,
         &exynos5_clk_mout_bpll,
+        &exynos5_clk_mout_bpll_fout,
         &exynos5_clk_mout_bpll_user,
         &exynos5_clk_mout_cpll,
         &exynos5_clk_mout_epll,
         &exynos5_clk_mout_mpll,
+        &exynos5_clk_mout_mpll_fout,
         &exynos5_clk_mout_mpll_user,
         &exynos5_clk_vpllsrc,
         &exynos5_clk_sclk_vpll,
@@ -1103,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
         &exynos5_clk_sclk_hdmi27m,
         &exynos5_clk_sclk_hdmiphy,
         &clk_fout_bpll,
+        &clk_fout_bpll_div2,
         &clk_fout_cpll,
+        &clk_fout_mpll_div2,
         &exynos5_clk_armclk,
 };
 
@@ -1268,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
         clk_fout_apll.ops = &exynos5_fout_apll_ops;
         clk_fout_bpll.rate = bpll;
+        clk_fout_bpll_div2.rate = bpll >> 1;
         clk_fout_cpll.rate = cpll;
         clk_fout_mpll.rate = mpll;
+        clk_fout_mpll_div2.rate = mpll >> 1;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
 #define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
 
+#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)