aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-exynos
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2012-01-07 06:51:28 -0500
committerArnd Bergmann <arnd@arndb.de>2012-01-07 06:51:28 -0500
commit40ba95fdf158713377d47736b1b3a9d75f4f2515 (patch)
tree17a3216542d1107f777fd82577c91aebbce597d6 /arch/arm/mach-exynos
parent70d84a6431d732cbc4e68e72b6890cdd3865d43d (diff)
parent0575fb754dbfc32a01f297e778533340a533ec68 (diff)
Merge branch 'depends/rmk/restart' into next/cleanup
Conflicts: arch/arm/mach-at91/at91cap9.c arch/arm/mach-at91/at91sam9260.c arch/arm/mach-at91/at91sam9261.c arch/arm/mach-at91/at91sam9263.c arch/arm/mach-at91/at91sam9g45.c arch/arm/mach-at91/at91sam9rl.c arch/arm/mach-exynos/cpu.c arch/arm/mach-shmobile/board-kota2.c This resolves a bunch of conflicts between the arm-soc tree and changes from the arm tree that have gone upstream. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Makefile9
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c3
-rw-r--r--arch/arm/mach-exynos/clock.c3
-rw-r--r--arch/arm/mach-exynos/common.c704
-rw-r--r--arch/arm/mach-exynos/common.h41
-rw-r--r--arch/arm/mach-exynos/cpu.c284
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h2
-rw-r--r--arch/arm/mach-exynos/init.c42
-rw-r--r--arch/arm/mach-exynos/irq-combiner.c124
-rw-r--r--arch/arm/mach-exynos/irq-eint.c237
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c6
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c6
-rw-r--r--arch/arm/mach-exynos/mach-origen.c6
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c7
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c7
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c6
-rw-r--r--arch/arm/mach-exynos/mct.c13
19 files changed, 794 insertions, 721 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 59069a35e40b..bcb9efc576e9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,15 +10,17 @@ obj-m :=
10obj-n := 10obj-n :=
11obj- := 11obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o 15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 21
22obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o
23
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 24obj-$(CONFIG_SMP) += platsmp.o headsmp.o
23 25
24obj-$(CONFIG_EXYNOS4_MCT) += mct.o 26obj-$(CONFIG_EXYNOS4_MCT) += mct.o
@@ -45,6 +47,7 @@ obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 47obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
46obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
47 49
50obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
48obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 51obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
49obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 52obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 53obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b9d5ef670eb4..a5823a7f249e 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4210_clock_save[] = { 35static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1), 37 SAVE_ITEM(S5P_CLKSRC_LCD1),
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 77d5decb34fd..26a668b0d101 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -23,7 +23,6 @@
23#include <plat/pll.h> 23#include <plat/pll.h>
24#include <plat/s5p-clock.h> 24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h> 25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h> 26#include <plat/pm.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -31,6 +30,8 @@
31#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h> 31#include <mach/exynos4-clock.h>
33 32
33#include "common.h"
34
34static struct sleep_save exynos4212_clock_save[] = { 35static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE), 36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5c..83616a039b15 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -21,7 +21,6 @@
21#include <plat/pll.h> 21#include <plat/pll.h>
22#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h> 24#include <plat/pm.h>
26 25
27#include <mach/map.h> 26#include <mach/map.h>
@@ -29,6 +28,8 @@
29#include <mach/sysmmu.h> 28#include <mach/sysmmu.h>
30#include <mach/exynos4-clock.h> 29#include <mach/exynos4-clock.h>
31 30
31#include "common.h"
32
32static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
new file mode 100644
index 000000000000..5de4214fa78f
--- /dev/null
+++ b/arch/arm/mach-exynos/common.c
@@ -0,0 +1,704 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/sysdev.h>
17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
20
21#include <asm/proc-fns.h>
22#include <asm/exception.h>
23#include <asm/hardware/cache-l2x0.h>
24#include <asm/hardware/gic.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <mach/regs-irq.h>
29#include <mach/regs-pmu.h>
30#include <mach/regs-gpio.h>
31
32#include <plat/cpu.h>
33#include <plat/clock.h>
34#include <plat/devs.h>
35#include <plat/pm.h>
36#include <plat/sdhci.h>
37#include <plat/gpio-cfg.h>
38#include <plat/adc-core.h>
39#include <plat/fb-core.h>
40#include <plat/fimc-core.h>
41#include <plat/iic-core.h>
42#include <plat/tv-core.h>
43#include <plat/regs-serial.h>
44
45#include "common.h"
46
47static const char name_exynos4210[] = "EXYNOS4210";
48static const char name_exynos4212[] = "EXYNOS4212";
49static const char name_exynos4412[] = "EXYNOS4412";
50
51static struct cpu_table cpu_ids[] __initdata = {
52 {
53 .idcode = EXYNOS4210_CPU_ID,
54 .idmask = EXYNOS4_CPU_MASK,
55 .map_io = exynos4_map_io,
56 .init_clocks = exynos4_init_clocks,
57 .init_uarts = exynos4_init_uarts,
58 .init = exynos_init,
59 .name = name_exynos4210,
60 }, {
61 .idcode = EXYNOS4212_CPU_ID,
62 .idmask = EXYNOS4_CPU_MASK,
63 .map_io = exynos4_map_io,
64 .init_clocks = exynos4_init_clocks,
65 .init_uarts = exynos4_init_uarts,
66 .init = exynos_init,
67 .name = name_exynos4212,
68 }, {
69 .idcode = EXYNOS4412_CPU_ID,
70 .idmask = EXYNOS4_CPU_MASK,
71 .map_io = exynos4_map_io,
72 .init_clocks = exynos4_init_clocks,
73 .init_uarts = exynos4_init_uarts,
74 .init = exynos_init,
75 .name = name_exynos4412,
76 },
77};
78
79/* Initial IO mappings */
80
81static struct map_desc exynos_iodesc[] __initdata = {
82 {
83 .virtual = (unsigned long)S5P_VA_CHIPID,
84 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
85 .length = SZ_4K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = (unsigned long)S3C_VA_SYS,
89 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
90 .length = SZ_64K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (unsigned long)S3C_VA_TIMER,
94 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
95 .length = SZ_16K,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = (unsigned long)S3C_VA_WATCHDOG,
99 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
100 .length = SZ_4K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (unsigned long)S5P_VA_SROMC,
104 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
105 .length = SZ_4K,
106 .type = MT_DEVICE,
107 }, {
108 .virtual = (unsigned long)S5P_VA_SYSTIMER,
109 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
110 .length = SZ_4K,
111 .type = MT_DEVICE,
112 }, {
113 .virtual = (unsigned long)S5P_VA_PMU,
114 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
115 .length = SZ_64K,
116 .type = MT_DEVICE,
117 }, {
118 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
119 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
120 .length = SZ_4K,
121 .type = MT_DEVICE,
122 }, {
123 .virtual = (unsigned long)S5P_VA_GIC_CPU,
124 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
125 .length = SZ_64K,
126 .type = MT_DEVICE,
127 }, {
128 .virtual = (unsigned long)S5P_VA_GIC_DIST,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
130 .length = SZ_64K,
131 .type = MT_DEVICE,
132 }, {
133 .virtual = (unsigned long)S3C_VA_UART,
134 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
135 .length = SZ_512K,
136 .type = MT_DEVICE,
137 },
138};
139
140static struct map_desc exynos4_iodesc[] __initdata = {
141 {
142 .virtual = (unsigned long)S5P_VA_CMU,
143 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
144 .length = SZ_128K,
145 .type = MT_DEVICE,
146 }, {
147 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
148 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
149 .length = SZ_8K,
150 .type = MT_DEVICE,
151 }, {
152 .virtual = (unsigned long)S5P_VA_L2CC,
153 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
154 .length = SZ_4K,
155 .type = MT_DEVICE,
156 }, {
157 .virtual = (unsigned long)S5P_VA_GPIO1,
158 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
159 .length = SZ_4K,
160 .type = MT_DEVICE,
161 }, {
162 .virtual = (unsigned long)S5P_VA_GPIO2,
163 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
164 .length = SZ_4K,
165 .type = MT_DEVICE,
166 }, {
167 .virtual = (unsigned long)S5P_VA_GPIO3,
168 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
169 .length = SZ_256,
170 .type = MT_DEVICE,
171 }, {
172 .virtual = (unsigned long)S5P_VA_DMC0,
173 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
174 .length = SZ_4K,
175 .type = MT_DEVICE,
176 }, {
177 .virtual = (unsigned long)S5P_VA_SROMC,
178 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
179 .length = SZ_4K,
180 .type = MT_DEVICE,
181 }, {
182 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
183 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
184 .length = SZ_4K,
185 .type = MT_DEVICE,
186 },
187};
188
189static struct map_desc exynos4_iodesc0[] __initdata = {
190 {
191 .virtual = (unsigned long)S5P_VA_SYSRAM,
192 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
193 .length = SZ_4K,
194 .type = MT_DEVICE,
195 },
196};
197
198static struct map_desc exynos4_iodesc1[] __initdata = {
199 {
200 .virtual = (unsigned long)S5P_VA_SYSRAM,
201 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
202 .length = SZ_4K,
203 .type = MT_DEVICE,
204 },
205};
206
207static void exynos_idle(void)
208{
209 if (!need_resched())
210 cpu_do_idle();
211
212 local_irq_enable();
213}
214
215void exynos4_restart(char mode, const char *cmd)
216{
217 __raw_writel(0x1, S5P_SWRESET);
218}
219
220/*
221 * exynos_map_io
222 *
223 * register the standard cpu IO areas
224 */
225
226void __init exynos_init_io(struct map_desc *mach_desc, int size)
227{
228 /* initialize the io descriptors we need for initialization */
229 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
230 if (mach_desc)
231 iotable_init(mach_desc, size);
232
233 /* detect cpu id and rev. */
234 s5p_init_cpu(S5P_VA_CHIPID);
235
236 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
237}
238
239void __init exynos4_map_io(void)
240{
241 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
242
243 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
244 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
245 else
246 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
247
248 /* initialize device information early */
249 exynos4_default_sdhci0();
250 exynos4_default_sdhci1();
251 exynos4_default_sdhci2();
252 exynos4_default_sdhci3();
253
254 s3c_adc_setname("samsung-adc-v3");
255
256 s3c_fimc_setname(0, "exynos4-fimc");
257 s3c_fimc_setname(1, "exynos4-fimc");
258 s3c_fimc_setname(2, "exynos4-fimc");
259 s3c_fimc_setname(3, "exynos4-fimc");
260
261 /* The I2C bus controllers are directly compatible with s3c2440 */
262 s3c_i2c0_setname("s3c2440-i2c");
263 s3c_i2c1_setname("s3c2440-i2c");
264 s3c_i2c2_setname("s3c2440-i2c");
265
266 s5p_fb_setname(0, "exynos4-fb");
267 s5p_hdmi_setname("exynos4-hdmi");
268}
269
270void __init exynos4_init_clocks(int xtal)
271{
272 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
273
274 s3c24xx_register_baseclocks(xtal);
275 s5p_register_clocks(xtal);
276
277 if (soc_is_exynos4210())
278 exynos4210_register_clocks();
279 else if (soc_is_exynos4212() || soc_is_exynos4412())
280 exynos4212_register_clocks();
281
282 exynos4_register_clocks();
283 exynos4_setup_clocks();
284}
285
286#define COMBINER_ENABLE_SET 0x0
287#define COMBINER_ENABLE_CLEAR 0x4
288#define COMBINER_INT_STATUS 0xC
289
290static DEFINE_SPINLOCK(irq_controller_lock);
291
292struct combiner_chip_data {
293 unsigned int irq_offset;
294 unsigned int irq_mask;
295 void __iomem *base;
296};
297
298static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
299
300static inline void __iomem *combiner_base(struct irq_data *data)
301{
302 struct combiner_chip_data *combiner_data =
303 irq_data_get_irq_chip_data(data);
304
305 return combiner_data->base;
306}
307
308static void combiner_mask_irq(struct irq_data *data)
309{
310 u32 mask = 1 << (data->irq % 32);
311
312 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
313}
314
315static void combiner_unmask_irq(struct irq_data *data)
316{
317 u32 mask = 1 << (data->irq % 32);
318
319 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
320}
321
322static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
323{
324 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
325 struct irq_chip *chip = irq_get_chip(irq);
326 unsigned int cascade_irq, combiner_irq;
327 unsigned long status;
328
329 chained_irq_enter(chip, desc);
330
331 spin_lock(&irq_controller_lock);
332 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
333 spin_unlock(&irq_controller_lock);
334 status &= chip_data->irq_mask;
335
336 if (status == 0)
337 goto out;
338
339 combiner_irq = __ffs(status);
340
341 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
342 if (unlikely(cascade_irq >= NR_IRQS))
343 do_bad_IRQ(cascade_irq, desc);
344 else
345 generic_handle_irq(cascade_irq);
346
347 out:
348 chained_irq_exit(chip, desc);
349}
350
351static struct irq_chip combiner_chip = {
352 .name = "COMBINER",
353 .irq_mask = combiner_mask_irq,
354 .irq_unmask = combiner_unmask_irq,
355};
356
357static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
358{
359 if (combiner_nr >= MAX_COMBINER_NR)
360 BUG();
361 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
362 BUG();
363 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
364}
365
366static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
367 unsigned int irq_start)
368{
369 unsigned int i;
370
371 if (combiner_nr >= MAX_COMBINER_NR)
372 BUG();
373
374 combiner_data[combiner_nr].base = base;
375 combiner_data[combiner_nr].irq_offset = irq_start;
376 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
377
378 /* Disable all interrupts */
379
380 __raw_writel(combiner_data[combiner_nr].irq_mask,
381 base + COMBINER_ENABLE_CLEAR);
382
383 /* Setup the Linux IRQ subsystem */
384
385 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
386 + MAX_IRQ_IN_COMBINER; i++) {
387 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
388 irq_set_chip_data(i, &combiner_data[combiner_nr]);
389 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
390 }
391}
392
393void __init exynos4_init_irq(void)
394{
395 int irq;
396 unsigned int gic_bank_offset;
397
398 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
399
400 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
401
402 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
403
404 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
405 COMBINER_IRQ(irq, 0));
406 combiner_cascade_irq(irq, IRQ_SPI(irq));
407 }
408
409 /*
410 * The parameters of s5p_init_irq() are for VIC init.
411 * Theses parameters should be NULL and 0 because EXYNOS4
412 * uses GIC instead of VIC.
413 */
414 s5p_init_irq(NULL, 0);
415}
416
417struct sysdev_class exynos4_sysclass = {
418 .name = "exynos4-core",
419};
420
421static struct sys_device exynos4_sysdev = {
422 .cls = &exynos4_sysclass,
423};
424
425static int __init exynos4_core_init(void)
426{
427 return sysdev_class_register(&exynos4_sysclass);
428}
429core_initcall(exynos4_core_init);
430
431#ifdef CONFIG_CACHE_L2X0
432static int __init exynos4_l2x0_cache_init(void)
433{
434 /* TAG, Data Latency Control: 2cycle */
435 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
436
437 if (soc_is_exynos4210())
438 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
439 else if (soc_is_exynos4212() || soc_is_exynos4412())
440 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
441
442 /* L2X0 Prefetch Control */
443 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
444
445 /* L2X0 Power Control */
446 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
447 S5P_VA_L2CC + L2X0_POWER_CTRL);
448
449 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
450
451 return 0;
452}
453
454early_initcall(exynos4_l2x0_cache_init);
455#endif
456
457int __init exynos_init(void)
458{
459 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
460
461 /* set idle function */
462 pm_idle = exynos_idle;
463
464 return sysdev_register(&exynos4_sysdev);
465}
466
467static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
468 [0] = {
469 .name = "uclk1",
470 .divisor = 1,
471 .min_baud = 0,
472 .max_baud = 0,
473 },
474};
475
476/* uart registration process */
477
478void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
479{
480 struct s3c2410_uartcfg *tcfg = cfg;
481 u32 ucnt;
482
483 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
484 if (!tcfg->clocks) {
485 tcfg->has_fracval = 1;
486 tcfg->clocks = exynos4_serial_clocks;
487 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
488 }
489 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
490 }
491
492 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
493}
494
495static DEFINE_SPINLOCK(eint_lock);
496
497static unsigned int eint0_15_data[16];
498
499static unsigned int exynos4_get_irq_nr(unsigned int number)
500{
501 u32 ret = 0;
502
503 switch (number) {
504 case 0 ... 3:
505 ret = (number + IRQ_EINT0);
506 break;
507 case 4 ... 7:
508 ret = (number + (IRQ_EINT4 - 4));
509 break;
510 case 8 ... 15:
511 ret = (number + (IRQ_EINT8 - 8));
512 break;
513 default:
514 printk(KERN_ERR "number available : %d\n", number);
515 }
516
517 return ret;
518}
519
520static inline void exynos4_irq_eint_mask(struct irq_data *data)
521{
522 u32 mask;
523
524 spin_lock(&eint_lock);
525 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
526 mask |= eint_irq_to_bit(data->irq);
527 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
528 spin_unlock(&eint_lock);
529}
530
531static void exynos4_irq_eint_unmask(struct irq_data *data)
532{
533 u32 mask;
534
535 spin_lock(&eint_lock);
536 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
537 mask &= ~(eint_irq_to_bit(data->irq));
538 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
539 spin_unlock(&eint_lock);
540}
541
542static inline void exynos4_irq_eint_ack(struct irq_data *data)
543{
544 __raw_writel(eint_irq_to_bit(data->irq),
545 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
546}
547
548static void exynos4_irq_eint_maskack(struct irq_data *data)
549{
550 exynos4_irq_eint_mask(data);
551 exynos4_irq_eint_ack(data);
552}
553
554static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
555{
556 int offs = EINT_OFFSET(data->irq);
557 int shift;
558 u32 ctrl, mask;
559 u32 newvalue = 0;
560
561 switch (type) {
562 case IRQ_TYPE_EDGE_RISING:
563 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
564 break;
565
566 case IRQ_TYPE_EDGE_FALLING:
567 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
568 break;
569
570 case IRQ_TYPE_EDGE_BOTH:
571 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
572 break;
573
574 case IRQ_TYPE_LEVEL_LOW:
575 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
576 break;
577
578 case IRQ_TYPE_LEVEL_HIGH:
579 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
580 break;
581
582 default:
583 printk(KERN_ERR "No such irq type %d", type);
584 return -EINVAL;
585 }
586
587 shift = (offs & 0x7) * 4;
588 mask = 0x7 << shift;
589
590 spin_lock(&eint_lock);
591 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
592 ctrl &= ~mask;
593 ctrl |= newvalue << shift;
594 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
595 spin_unlock(&eint_lock);
596
597 switch (offs) {
598 case 0 ... 7:
599 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
600 break;
601 case 8 ... 15:
602 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
603 break;
604 case 16 ... 23:
605 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
606 break;
607 case 24 ... 31:
608 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
609 break;
610 default:
611 printk(KERN_ERR "No such irq number %d", offs);
612 }
613
614 return 0;
615}
616
617static struct irq_chip exynos4_irq_eint = {
618 .name = "exynos4-eint",
619 .irq_mask = exynos4_irq_eint_mask,
620 .irq_unmask = exynos4_irq_eint_unmask,
621 .irq_mask_ack = exynos4_irq_eint_maskack,
622 .irq_ack = exynos4_irq_eint_ack,
623 .irq_set_type = exynos4_irq_eint_set_type,
624#ifdef CONFIG_PM
625 .irq_set_wake = s3c_irqext_wake,
626#endif
627};
628
629/*
630 * exynos4_irq_demux_eint
631 *
632 * This function demuxes the IRQ from from EINTs 16 to 31.
633 * It is designed to be inlined into the specific handler
634 * s5p_irq_demux_eintX_Y.
635 *
636 * Each EINT pend/mask registers handle eight of them.
637 */
638static inline void exynos4_irq_demux_eint(unsigned int start)
639{
640 unsigned int irq;
641
642 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
643 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
644
645 status &= ~mask;
646 status &= 0xff;
647
648 while (status) {
649 irq = fls(status) - 1;
650 generic_handle_irq(irq + start);
651 status &= ~(1 << irq);
652 }
653}
654
655static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
656{
657 struct irq_chip *chip = irq_get_chip(irq);
658 chained_irq_enter(chip, desc);
659 exynos4_irq_demux_eint(IRQ_EINT(16));
660 exynos4_irq_demux_eint(IRQ_EINT(24));
661 chained_irq_exit(chip, desc);
662}
663
664static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
665{
666 u32 *irq_data = irq_get_handler_data(irq);
667 struct irq_chip *chip = irq_get_chip(irq);
668
669 chained_irq_enter(chip, desc);
670 chip->irq_mask(&desc->irq_data);
671
672 if (chip->irq_ack)
673 chip->irq_ack(&desc->irq_data);
674
675 generic_handle_irq(*irq_data);
676
677 chip->irq_unmask(&desc->irq_data);
678 chained_irq_exit(chip, desc);
679}
680
681int __init exynos4_init_irq_eint(void)
682{
683 int irq;
684
685 for (irq = 0 ; irq <= 31 ; irq++) {
686 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
687 handle_level_irq);
688 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
689 }
690
691 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
692
693 for (irq = 0 ; irq <= 15 ; irq++) {
694 eint0_15_data[irq] = IRQ_EINT(irq);
695
696 irq_set_handler_data(exynos4_get_irq_nr(irq),
697 &eint0_15_data[irq]);
698 irq_set_chained_handler(exynos4_get_irq_nr(irq),
699 exynos4_irq_eint0_15);
700 }
701
702 return 0;
703}
704arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
new file mode 100644
index 000000000000..1ac49de0f398
--- /dev/null
+++ b/arch/arm/mach-exynos/common.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for EXYNOS machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14
15void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void);
17
18void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void);
20
21void exynos4210_register_clocks(void);
22void exynos4212_register_clocks(void);
23
24void exynos4_restart(char mode, const char *cmd);
25
26extern struct sys_timer exynos4_timer;
27
28#ifdef CONFIG_ARCH_EXYNOS
29extern int exynos_init(void);
30extern void exynos4_map_io(void);
31extern void exynos4_init_clocks(int xtal);
32extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
33
34#else
35#define exynos4_init_clocks NULL
36#define exynos4_init_uarts NULL
37#define exynos4_map_io NULL
38#define exynos_init NULL
39#endif
40
41#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
deleted file mode 100644
index 22316cb31a8c..000000000000
--- a/arch/arm/mach-exynos/cpu.c
+++ /dev/null
@@ -1,284 +0,0 @@
1/* linux/arch/arm/mach-exynos/cpu.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/exception.h>
19#include <asm/hardware/cache-l2x0.h>
20#include <asm/hardware/gic.h>
21
22#include <plat/cpu.h>
23#include <plat/clock.h>
24#include <plat/devs.h>
25#include <plat/exynos4.h>
26#include <plat/adc-core.h>
27#include <plat/sdhci.h>
28#include <plat/fb-core.h>
29#include <plat/fimc-core.h>
30#include <plat/iic-core.h>
31#include <plat/reset.h>
32#include <plat/tv-core.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-pmu.h>
36
37extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
38 unsigned int irq_start);
39extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
40
41/* Initial IO mappings */
42static struct map_desc exynos_iodesc[] __initdata = {
43 {
44 .virtual = (unsigned long)S5P_VA_SYSTIMER,
45 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
46 .length = SZ_4K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long)S5P_VA_PMU,
50 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
51 .length = SZ_64K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
55 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)S5P_VA_GIC_CPU,
60 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
61 .length = SZ_64K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (unsigned long)S5P_VA_GIC_DIST,
65 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
66 .length = SZ_64K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (unsigned long)S3C_VA_UART,
70 .pfn = __phys_to_pfn(S3C_PA_UART),
71 .length = SZ_512K,
72 .type = MT_DEVICE,
73 },
74};
75
76static struct map_desc exynos4_iodesc[] __initdata = {
77 {
78 .virtual = (unsigned long)S5P_VA_CMU,
79 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
80 .length = SZ_128K,
81 .type = MT_DEVICE,
82 }, {
83 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
84 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
85 .length = SZ_8K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = (unsigned long)S5P_VA_L2CC,
89 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
90 .length = SZ_4K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (unsigned long)S5P_VA_GPIO1,
94 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
95 .length = SZ_4K,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = (unsigned long)S5P_VA_GPIO2,
99 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
100 .length = SZ_4K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (unsigned long)S5P_VA_GPIO3,
104 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
105 .length = SZ_256,
106 .type = MT_DEVICE,
107 }, {
108 .virtual = (unsigned long)S5P_VA_DMC0,
109 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
110 .length = SZ_4K,
111 .type = MT_DEVICE,
112 }, {
113 .virtual = (unsigned long)S5P_VA_SROMC,
114 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
115 .length = SZ_4K,
116 .type = MT_DEVICE,
117 }, {
118 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
119 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
120 .length = SZ_4K,
121 .type = MT_DEVICE,
122 },
123};
124
125static struct map_desc exynos4_iodesc0[] __initdata = {
126 {
127 .virtual = (unsigned long)S5P_VA_SYSRAM,
128 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
129 .length = SZ_4K,
130 .type = MT_DEVICE,
131 },
132};
133
134static struct map_desc exynos4_iodesc1[] __initdata = {
135 {
136 .virtual = (unsigned long)S5P_VA_SYSRAM,
137 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
138 .length = SZ_4K,
139 .type = MT_DEVICE,
140 },
141};
142
143static void exynos_idle(void)
144{
145 if (!need_resched())
146 cpu_do_idle();
147
148 local_irq_enable();
149}
150
151static void exynos4_sw_reset(void)
152{
153 __raw_writel(0x1, S5P_SWRESET);
154}
155
156/*
157 * exynos_map_io
158 *
159 * register the standard cpu IO areas
160 */
161void __init exynos4_map_io(void)
162{
163 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
164 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
165
166 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
167 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
168 else
169 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
170
171 /* initialize device information early */
172 exynos4_default_sdhci0();
173 exynos4_default_sdhci1();
174 exynos4_default_sdhci2();
175 exynos4_default_sdhci3();
176
177 s3c_adc_setname("samsung-adc-v3");
178
179 s3c_fimc_setname(0, "exynos4-fimc");
180 s3c_fimc_setname(1, "exynos4-fimc");
181 s3c_fimc_setname(2, "exynos4-fimc");
182 s3c_fimc_setname(3, "exynos4-fimc");
183
184 /* The I2C bus controllers are directly compatible with s3c2440 */
185 s3c_i2c0_setname("s3c2440-i2c");
186 s3c_i2c1_setname("s3c2440-i2c");
187 s3c_i2c2_setname("s3c2440-i2c");
188
189 s5p_fb_setname(0, "exynos4-fb");
190 s5p_hdmi_setname("exynos4-hdmi");
191}
192
193void __init exynos4_init_clocks(int xtal)
194{
195 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
196
197 s3c24xx_register_baseclocks(xtal);
198 s5p_register_clocks(xtal);
199
200 if (soc_is_exynos4210())
201 exynos4210_register_clocks();
202 else if (soc_is_exynos4212() || soc_is_exynos4412())
203 exynos4212_register_clocks();
204
205 exynos4_register_clocks();
206 exynos4_setup_clocks();
207}
208
209void __init exynos4_init_irq(void)
210{
211 int irq;
212 unsigned int gic_bank_offset;
213
214 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
215
216 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
217
218 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
219
220 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
221 COMBINER_IRQ(irq, 0));
222 combiner_cascade_irq(irq, IRQ_SPI(irq));
223 }
224
225 /* The parameters of s5p_init_irq() are for VIC init.
226 * Theses parameters should be NULL and 0 because EXYNOS4
227 * uses GIC instead of VIC.
228 */
229 s5p_init_irq(NULL, 0);
230}
231
232struct sysdev_class exynos4_sysclass = {
233 .name = "exynos4-core",
234};
235
236static struct sys_device exynos4_sysdev = {
237 .cls = &exynos4_sysclass,
238};
239
240static int __init exynos4_core_init(void)
241{
242 return sysdev_class_register(&exynos4_sysclass);
243}
244core_initcall(exynos4_core_init);
245
246#ifdef CONFIG_CACHE_L2X0
247static int __init exynos4_l2x0_cache_init(void)
248{
249 /* TAG, Data Latency Control: 2cycle */
250 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
251
252 if (soc_is_exynos4210())
253 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
254 else if (soc_is_exynos4212() || soc_is_exynos4412())
255 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
256
257 /* L2X0 Prefetch Control */
258 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
259
260 /* L2X0 Power Control */
261 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
262 S5P_VA_L2CC + L2X0_POWER_CTRL);
263
264 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
265
266 return 0;
267}
268
269early_initcall(exynos4_l2x0_cache_init);
270#endif
271
272int __init exynos_init(void)
273{
274 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
275
276 /* set idle function */
277 pm_idle = exynos_idle;
278
279 /* set sw_reset function */
280 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
281 s5p_reset_hook = exynos4_sw_reset;
282
283 return sysdev_register(&exynos4_sysdev);
284}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af0..d1829860a0ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -149,7 +149,6 @@
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 150#define S3C_PA_UART EXYNOS4_PA_UART
151 151
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI 152#define S5P_PA_EHCI EXYNOS4_PA_EHCI
154#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 153#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
155#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 154#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
@@ -166,26 +165,17 @@
166#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 165#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
167#define S5P_PA_SDO EXYNOS4_PA_SDO 166#define S5P_PA_SDO EXYNOS4_PA_SDO
168#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 167#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
169#define S5P_PA_SROMC EXYNOS4_PA_SROMC
170#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
171#define S5P_PA_TIMER EXYNOS4_PA_TIMER
172#define S5P_PA_VP EXYNOS4_PA_VP 168#define S5P_PA_VP EXYNOS4_PA_VP
173 169
174#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 170#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
175#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 171#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
176#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 172#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
177 173
178#define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
179#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
180#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
181#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
182#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
183
184/* Compatibility UART */ 174/* Compatibility UART */
185 175
186#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 176#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
187 177
188#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 178#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
189#define S5P_PA_UART0 S5P_PA_UART(0) 179#define S5P_PA_UART0 S5P_PA_UART(0)
190#define S5P_PA_UART1 S5P_PA_UART(1) 180#define S5P_PA_UART1 S5P_PA_UART(1)
191#define S5P_PA_UART2 S5P_PA_UART(2) 181#define S5P_PA_UART2 S5P_PA_UART(2)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 5e3220c18fc7..0063a6de3dc8 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -13,8 +13,6 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16#include <plat/system-reset.h>
17
18static void arch_idle(void) 16static void arch_idle(void)
19{ 17{
20 /* nothing here yet */ 18 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
deleted file mode 100644
index a8a83e3881a4..000000000000
--- a/arch/arm/mach-exynos/init.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-exynos4/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */
27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{
29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt;
31
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1;
35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 }
38 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
39 }
40
41 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
42}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
deleted file mode 100644
index 5a2758ab055e..000000000000
--- a/arch/arm/mach-exynos/irq-combiner.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 unsigned int irq_mask;
28 void __iomem *base;
29};
30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32
33static inline void __iomem *combiner_base(struct irq_data *data)
34{
35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
38 return combiner_data->base;
39}
40
41static void combiner_mask_irq(struct irq_data *data)
42{
43 u32 mask = 1 << (data->irq % 32);
44
45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
46}
47
48static void combiner_unmask_irq(struct irq_data *data)
49{
50 u32 mask = 1 << (data->irq % 32);
51
52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
53}
54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{
57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status;
61
62 chained_irq_enter(chip, desc);
63
64 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock);
67 status &= chip_data->irq_mask;
68
69 if (status == 0)
70 goto out;
71
72 combiner_irq = __ffs(status);
73
74 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
75 if (unlikely(cascade_irq >= NR_IRQS))
76 do_bad_IRQ(cascade_irq, desc);
77 else
78 generic_handle_irq(cascade_irq);
79
80 out:
81 chained_irq_exit(chip, desc);
82}
83
84static struct irq_chip combiner_chip = {
85 .name = "COMBINER",
86 .irq_mask = combiner_mask_irq,
87 .irq_unmask = combiner_unmask_irq,
88};
89
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
91{
92 if (combiner_nr >= MAX_COMBINER_NR)
93 BUG();
94 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
95 BUG();
96 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
97}
98
99void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
100 unsigned int irq_start)
101{
102 unsigned int i;
103
104 if (combiner_nr >= MAX_COMBINER_NR)
105 BUG();
106
107 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start;
109 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
110
111 /* Disable all interrupts */
112
113 __raw_writel(combiner_data[combiner_nr].irq_mask,
114 base + COMBINER_ENABLE_CLEAR);
115
116 /* Setup the Linux IRQ subsystem */
117
118 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
119 + MAX_IRQ_IN_COMBINER; i++) {
120 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
121 irq_set_chip_data(i, &combiner_data[combiner_nr]);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 }
124}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
deleted file mode 100644
index badb8c66fc9b..000000000000
--- a/arch/arm/mach-exynos/irq-eint.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26#include <asm/mach/irq.h>
27
28static DEFINE_SPINLOCK(eint_lock);
29
30static unsigned int eint0_15_data[16];
31
32static unsigned int exynos4_get_irq_nr(unsigned int number)
33{
34 u32 ret = 0;
35
36 switch (number) {
37 case 0 ... 3:
38 ret = (number + IRQ_EINT0);
39 break;
40 case 4 ... 7:
41 ret = (number + (IRQ_EINT4 - 4));
42 break;
43 case 8 ... 15:
44 ret = (number + (IRQ_EINT8 - 8));
45 break;
46 default:
47 printk(KERN_ERR "number available : %d\n", number);
48 }
49
50 return ret;
51}
52
53static inline void exynos4_irq_eint_mask(struct irq_data *data)
54{
55 u32 mask;
56
57 spin_lock(&eint_lock);
58 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 mask |= eint_irq_to_bit(data->irq);
60 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
61 spin_unlock(&eint_lock);
62}
63
64static void exynos4_irq_eint_unmask(struct irq_data *data)
65{
66 u32 mask;
67
68 spin_lock(&eint_lock);
69 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 mask &= ~(eint_irq_to_bit(data->irq));
71 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
72 spin_unlock(&eint_lock);
73}
74
75static inline void exynos4_irq_eint_ack(struct irq_data *data)
76{
77 __raw_writel(eint_irq_to_bit(data->irq),
78 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
79}
80
81static void exynos4_irq_eint_maskack(struct irq_data *data)
82{
83 exynos4_irq_eint_mask(data);
84 exynos4_irq_eint_ack(data);
85}
86
87static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
88{
89 int offs = EINT_OFFSET(data->irq);
90 int shift;
91 u32 ctrl, mask;
92 u32 newvalue = 0;
93
94 switch (type) {
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -EINVAL;
118 }
119
120 shift = (offs & 0x7) * 4;
121 mask = 0x7 << shift;
122
123 spin_lock(&eint_lock);
124 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 ctrl &= ~mask;
126 ctrl |= newvalue << shift;
127 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
128 spin_unlock(&eint_lock);
129
130 switch (offs) {
131 case 0 ... 7:
132 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
133 break;
134 case 8 ... 15:
135 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
136 break;
137 case 16 ... 23:
138 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
139 break;
140 case 24 ... 31:
141 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
142 break;
143 default:
144 printk(KERN_ERR "No such irq number %d", offs);
145 }
146
147 return 0;
148}
149
150static struct irq_chip exynos4_irq_eint = {
151 .name = "exynos4-eint",
152 .irq_mask = exynos4_irq_eint_mask,
153 .irq_unmask = exynos4_irq_eint_unmask,
154 .irq_mask_ack = exynos4_irq_eint_maskack,
155 .irq_ack = exynos4_irq_eint_ack,
156 .irq_set_type = exynos4_irq_eint_set_type,
157#ifdef CONFIG_PM
158 .irq_set_wake = s3c_irqext_wake,
159#endif
160};
161
162/* exynos4_irq_demux_eint
163 *
164 * This function demuxes the IRQ from from EINTs 16 to 31.
165 * It is designed to be inlined into the specific handler
166 * s5p_irq_demux_eintX_Y.
167 *
168 * Each EINT pend/mask registers handle eight of them.
169 */
170static inline void exynos4_irq_demux_eint(unsigned int start)
171{
172 unsigned int irq;
173
174 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
175 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
176
177 status &= ~mask;
178 status &= 0xff;
179
180 while (status) {
181 irq = fls(status) - 1;
182 generic_handle_irq(irq + start);
183 status &= ~(1 << irq);
184 }
185}
186
187static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
188{
189 struct irq_chip *chip = irq_get_chip(irq);
190 chained_irq_enter(chip, desc);
191 exynos4_irq_demux_eint(IRQ_EINT(16));
192 exynos4_irq_demux_eint(IRQ_EINT(24));
193 chained_irq_exit(chip, desc);
194}
195
196static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
197{
198 u32 *irq_data = irq_get_handler_data(irq);
199 struct irq_chip *chip = irq_get_chip(irq);
200
201 chained_irq_enter(chip, desc);
202 chip->irq_mask(&desc->irq_data);
203
204 if (chip->irq_ack)
205 chip->irq_ack(&desc->irq_data);
206
207 generic_handle_irq(*irq_data);
208
209 chip->irq_unmask(&desc->irq_data);
210 chained_irq_exit(chip, desc);
211}
212
213int __init exynos4_init_irq_eint(void)
214{
215 int irq;
216
217 for (irq = 0 ; irq <= 31 ; irq++) {
218 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
219 handle_level_irq);
220 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
221 }
222
223 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
224
225 for (irq = 0 ; irq <= 15 ; irq++) {
226 eint0_15_data[irq] = IRQ_EINT(irq);
227
228 irq_set_handler_data(exynos4_get_irq_nr(irq),
229 &eint0_15_data[irq]);
230 irq_set_chained_handler(exynos4_get_irq_nr(irq),
231 exynos4_irq_eint0_15);
232 }
233
234 return 0;
235}
236
237arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 49da3089249a..d726fcd3acf9 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -21,7 +21,6 @@
21 21
22#include <plat/cpu.h> 22#include <plat/cpu.h>
23#include <plat/devs.h> 23#include <plat/devs.h>
24#include <plat/exynos4.h>
25#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
26#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
27#include <plat/regs-srom.h> 26#include <plat/regs-srom.h>
@@ -29,6 +28,8 @@
29 28
30#include <mach/map.h> 29#include <mach/map.h>
31 30
31#include "common.h"
32
32/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
33#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \ 35 S3C2410_UCON_RXILEVEL | \
@@ -188,7 +189,7 @@ static void __init armlex4210_smsc911x_init(void)
188 189
189static void __init armlex4210_map_io(void) 190static void __init armlex4210_map_io(void)
190{ 191{
191 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 192 exynos_init_io(NULL, 0);
192 s3c24xx_init_clocks(24000000); 193 s3c24xx_init_clocks(24000000);
193 s3c24xx_init_uarts(armlex4210_uartcfgs, 194 s3c24xx_init_uarts(armlex4210_uartcfgs,
194 ARRAY_SIZE(armlex4210_uartcfgs)); 195 ARRAY_SIZE(armlex4210_uartcfgs));
@@ -214,4 +215,5 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
214 .handle_irq = gic_handle_irq, 215 .handle_irq = gic_handle_irq,
215 .init_machine = armlex4210_machine_init, 216 .init_machine = armlex4210_machine_init,
216 .timer = &exynos4_timer, 217 .timer = &exynos4_timer,
218 .restart = exynos4_restart,
217MACHINE_END 219MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 5acec11821a4..635fb97e31ab 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -38,7 +38,6 @@
38#include <plat/adc.h> 38#include <plat/adc.h>
39#include <plat/regs-fb-v4.h> 39#include <plat/regs-fb-v4.h>
40#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <plat/exynos4.h>
42#include <plat/cpu.h> 41#include <plat/cpu.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/fb.h> 43#include <plat/fb.h>
@@ -55,6 +54,8 @@
55 54
56#include <mach/map.h> 55#include <mach/map.h>
57 56
57#include "common.h"
58
58/* Following are default values for UCON, ULCON and UFCON UART registers */ 59/* Following are default values for UCON, ULCON and UFCON UART registers */
59#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 60#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \ 61 S3C2410_UCON_RXILEVEL | \
@@ -1284,7 +1285,7 @@ static struct platform_device *nuri_devices[] __initdata = {
1284 1285
1285static void __init nuri_map_io(void) 1286static void __init nuri_map_io(void)
1286{ 1287{
1287 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 1288 exynos_init_io(NULL, 0);
1288 s3c24xx_init_clocks(24000000); 1289 s3c24xx_init_clocks(24000000);
1289 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1290 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1290} 1291}
@@ -1338,4 +1339,5 @@ MACHINE_START(NURI, "NURI")
1338 .init_machine = nuri_machine_init, 1339 .init_machine = nuri_machine_init,
1339 .timer = &exynos4_timer, 1340 .timer = &exynos4_timer,
1340 .reserve = &nuri_reserve, 1341 .reserve = &nuri_reserve,
1342 .restart = exynos4_restart,
1341MACHINE_END 1343MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5561b06c38ec..586eb995aa96 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -29,7 +29,6 @@
29 29
30#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
31#include <plat/regs-fb-v4.h> 31#include <plat/regs-fb-v4.h>
32#include <plat/exynos4.h>
33#include <plat/cpu.h> 32#include <plat/cpu.h>
34#include <plat/devs.h> 33#include <plat/devs.h>
35#include <plat/sdhci.h> 34#include <plat/sdhci.h>
@@ -44,6 +43,8 @@
44 43
45#include <mach/map.h> 44#include <mach/map.h>
46 45
46#include "common.h"
47
47/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
48#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
49 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -639,7 +640,7 @@ static void s5p_tv_setup(void)
639 640
640static void __init origen_map_io(void) 641static void __init origen_map_io(void)
641{ 642{
642 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 643 exynos_init_io(NULL, 0);
643 s3c24xx_init_clocks(24000000); 644 s3c24xx_init_clocks(24000000);
644 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 645 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
645} 646}
@@ -699,4 +700,5 @@ MACHINE_START(ORIGEN, "ORIGEN")
699 .init_machine = origen_machine_init, 700 .init_machine = origen_machine_init,
700 .timer = &exynos4_timer, 701 .timer = &exynos4_timer,
701 .reserve = &origen_reserve, 702 .reserve = &origen_reserve,
703 .restart = exynos4_restart,
702MACHINE_END 704MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 722d82d7f217..d00e4f016a68 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -28,7 +28,6 @@
28#include <plat/clock.h> 28#include <plat/clock.h>
29#include <plat/cpu.h> 29#include <plat/cpu.h>
30#include <plat/devs.h> 30#include <plat/devs.h>
31#include <plat/exynos4.h>
32#include <plat/gpio-cfg.h> 31#include <plat/gpio-cfg.h>
33#include <plat/iic.h> 32#include <plat/iic.h>
34#include <plat/keypad.h> 33#include <plat/keypad.h>
@@ -37,6 +36,8 @@
37 36
38#include <mach/map.h> 37#include <mach/map.h>
39 38
39#include "common.h"
40
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 41/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 42#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 43 S3C2410_UCON_RXILEVEL | \
@@ -250,7 +251,7 @@ static void __init smdk4x12_map_io(void)
250{ 251{
251 clk_xusbxti.rate = 24000000; 252 clk_xusbxti.rate = 24000000;
252 253
253 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 254 exynos_init_io(NULL, 0);
254 s3c24xx_init_clocks(clk_xusbxti.rate); 255 s3c24xx_init_clocks(clk_xusbxti.rate);
255 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 256 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
256} 257}
@@ -291,6 +292,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
291 .handle_irq = gic_handle_irq, 292 .handle_irq = gic_handle_irq,
292 .init_machine = smdk4x12_machine_init, 293 .init_machine = smdk4x12_machine_init,
293 .timer = &exynos4_timer, 294 .timer = &exynos4_timer,
295 .restart = exynos4_restart,
294MACHINE_END 296MACHINE_END
295 297
296MACHINE_START(SMDK4412, "SMDK4412") 298MACHINE_START(SMDK4412, "SMDK4412")
@@ -302,4 +304,5 @@ MACHINE_START(SMDK4412, "SMDK4412")
302 .handle_irq = gic_handle_irq, 304 .handle_irq = gic_handle_irq,
303 .init_machine = smdk4x12_machine_init, 305 .init_machine = smdk4x12_machine_init,
304 .timer = &exynos4_timer, 306 .timer = &exynos4_timer,
307 .restart = exynos4_restart,
305MACHINE_END 308MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index edc60b6108ed..5b365613b470 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -28,7 +28,6 @@
28#include <plat/regs-serial.h> 28#include <plat/regs-serial.h>
29#include <plat/regs-srom.h> 29#include <plat/regs-srom.h>
30#include <plat/regs-fb-v4.h> 30#include <plat/regs-fb-v4.h>
31#include <plat/exynos4.h>
32#include <plat/cpu.h> 31#include <plat/cpu.h>
33#include <plat/devs.h> 32#include <plat/devs.h>
34#include <plat/fb.h> 33#include <plat/fb.h>
@@ -44,6 +43,8 @@
44 43
45#include <mach/map.h> 44#include <mach/map.h>
46 45
46#include "common.h"
47
47/* Following are default values for UCON, ULCON and UFCON UART registers */ 48/* Following are default values for UCON, ULCON and UFCON UART registers */
48#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
49 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
@@ -333,7 +334,7 @@ static void s5p_tv_setup(void)
333 334
334static void __init smdkv310_map_io(void) 335static void __init smdkv310_map_io(void)
335{ 336{
336 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 337 exynos_init_io(NULL, 0);
337 s3c24xx_init_clocks(24000000); 338 s3c24xx_init_clocks(24000000);
338 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 339 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
339} 340}
@@ -380,6 +381,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
380 .init_machine = smdkv310_machine_init, 381 .init_machine = smdkv310_machine_init,
381 .timer = &exynos4_timer, 382 .timer = &exynos4_timer,
382 .reserve = &smdkv310_reserve, 383 .reserve = &smdkv310_reserve,
384 .restart = exynos4_restart,
383MACHINE_END 385MACHINE_END
384 386
385MACHINE_START(SMDKC210, "SMDKC210") 387MACHINE_START(SMDKC210, "SMDKC210")
@@ -390,4 +392,5 @@ MACHINE_START(SMDKC210, "SMDKC210")
390 .handle_irq = gic_handle_irq, 392 .handle_irq = gic_handle_irq,
391 .init_machine = smdkv310_machine_init, 393 .init_machine = smdkv310_machine_init,
392 .timer = &exynos4_timer, 394 .timer = &exynos4_timer,
395 .restart = exynos4_restart,
393MACHINE_END 396MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index cfc7d5076f5a..52aea972746a 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -28,7 +28,6 @@
28#include <asm/mach-types.h> 28#include <asm/mach-types.h>
29 29
30#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
31#include <plat/exynos4.h>
32#include <plat/cpu.h> 31#include <plat/cpu.h>
33#include <plat/devs.h> 32#include <plat/devs.h>
34#include <plat/iic.h> 33#include <plat/iic.h>
@@ -48,6 +47,8 @@
48#include <media/s5p_fimc.h> 47#include <media/s5p_fimc.h>
49#include <media/m5mols.h> 48#include <media/m5mols.h>
50 49
50#include "common.h"
51
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 52/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
53 S3C2410_UCON_RXILEVEL | \ 54 S3C2410_UCON_RXILEVEL | \
@@ -993,7 +994,7 @@ static struct platform_device *universal_devices[] __initdata = {
993 994
994static void __init universal_map_io(void) 995static void __init universal_map_io(void)
995{ 996{
996 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 997 exynos_init_io(NULL, 0);
997 s3c24xx_init_clocks(24000000); 998 s3c24xx_init_clocks(24000000);
998 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 999 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
999} 1000}
@@ -1063,4 +1064,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1063 .init_machine = universal_machine_init, 1064 .init_machine = universal_machine_init,
1064 .timer = &exynos4_timer, 1065 .timer = &exynos4_timer,
1065 .reserve = &universal_reserve, 1066 .reserve = &universal_reserve,
1067 .restart = exynos4_restart,
1066MACHINE_END 1068MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 97343df8f132..85b5527d0918 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -44,8 +44,6 @@ struct mct_clock_event_device {
44 char name[10]; 44 char name[10];
45}; 45};
46 46
47static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
48
49static void exynos4_mct_write(unsigned int value, void *addr) 47static void exynos4_mct_write(unsigned int value, void *addr)
50{ 48{
51 void __iomem *stat_addr; 49 void __iomem *stat_addr;
@@ -264,6 +262,9 @@ static void exynos4_clockevent_init(void)
264} 262}
265 263
266#ifdef CONFIG_LOCAL_TIMERS 264#ifdef CONFIG_LOCAL_TIMERS
265
266static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
267
267/* Clock event handling */ 268/* Clock event handling */
268static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 269static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
269{ 270{
@@ -428,9 +429,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
428 429
429void local_timer_stop(struct clock_event_device *evt) 430void local_timer_stop(struct clock_event_device *evt)
430{ 431{
432 unsigned int cpu = smp_processor_id();
431 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 433 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
432 if (mct_int_type == MCT_INT_SPI) 434 if (mct_int_type == MCT_INT_SPI)
433 disable_irq(evt->irq); 435 if (cpu == 0)
436 remove_irq(evt->irq, &mct_tick0_event_irq);
437 else
438 remove_irq(evt->irq, &mct_tick1_event_irq);
434 else 439 else
435 disable_percpu_irq(IRQ_MCT_LOCALTIMER); 440 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
436} 441}
@@ -443,6 +448,7 @@ static void __init exynos4_timer_resources(void)
443 448
444 clk_rate = clk_get_rate(mct_clk); 449 clk_rate = clk_get_rate(mct_clk);
445 450
451#ifdef CONFIG_LOCAL_TIMERS
446 if (mct_int_type == MCT_INT_PPI) { 452 if (mct_int_type == MCT_INT_PPI) {
447 int err; 453 int err;
448 454
@@ -452,6 +458,7 @@ static void __init exynos4_timer_resources(void)
452 WARN(err, "MCT: can't request IRQ %d (%d)\n", 458 WARN(err, "MCT: can't request IRQ %d (%d)\n",
453 IRQ_MCT_LOCALTIMER, err); 459 IRQ_MCT_LOCALTIMER, err);
454 } 460 }
461#endif /* CONFIG_LOCAL_TIMERS */
455} 462}
456 463
457static void __init exynos4_timer_init(void) 464static void __init exynos4_timer_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 17:39:37 -0500