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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
commitb3345d7c57d70e6cb6749af25cdbe80515582e99 (patch)
tree04cce706bc7e944ad1fb257108a8ae735948f97f /arch/arm/mach-exynos
parent44c916d58b9ef1f2c4aec2def57fa8289c716a60 (diff)
parentc2fff85e21818952aa0ee5778926beee6c03e579 (diff)
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/common.h14
-rw-r--r--arch/arm/mach-exynos/exynos.c30
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c106
-rw-r--r--arch/arm/mach-exynos/platsmp.c22
-rw-r--r--arch/arm/mach-exynos/pm.c61
-rw-r--r--arch/arm/mach-exynos/pmu.c40
-rw-r--r--arch/arm/mach-exynos/regs-pmu.h521
8 files changed, 415 insertions, 382 deletions
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9cc5617..47b904b3b973 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
134 134
135/* PMU(Power Management Unit) support */ 135/* PMU(Power Management Unit) support */
136 136
137#define PMU_TABLE_END NULL 137#define PMU_TABLE_END (-1U)
138 138
139enum sys_powerdown { 139enum sys_powerdown {
140 SYS_AFTR, 140 SYS_AFTR,
@@ -144,7 +144,7 @@ enum sys_powerdown {
144}; 144};
145 145
146struct exynos_pmu_conf { 146struct exynos_pmu_conf {
147 void __iomem *reg; 147 unsigned int offset;
148 unsigned int val[NUM_SYS_POWERDOWN]; 148 unsigned int val[NUM_SYS_POWERDOWN];
149}; 149};
150 150
@@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
160extern void s5p_init_cpu(void __iomem *cpuid_addr); 160extern void s5p_init_cpu(void __iomem *cpuid_addr);
161extern unsigned int samsung_rev(void); 161extern unsigned int samsung_rev(void);
162 162
163static inline void pmu_raw_writel(u32 val, u32 offset)
164{
165 __raw_writel(val, pmu_base_addr + offset);
166}
167
168static inline u32 pmu_raw_readl(u32 offset)
169{
170 return __raw_readl(pmu_base_addr + offset);
171}
172
163#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 173#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 3164ef2e6b6c..c426093bdbd9 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -61,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
61 .length = SZ_4K, 61 .length = SZ_4K,
62 .type = MT_DEVICE, 62 .type = MT_DEVICE,
63 }, { 63 }, {
64 .virtual = (unsigned long)S5P_VA_PMU,
65 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
66 .length = SZ_64K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 64 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
70 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), 65 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
71 .length = SZ_4K, 66 .length = SZ_4K,
@@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
139 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 134 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
140 .length = 144 * SZ_1K, 135 .length = 144 * SZ_1K,
141 .type = MT_DEVICE, 136 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S5P_VA_PMU,
144 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
145 .length = SZ_64K,
146 .type = MT_DEVICE,
147 }, 137 },
148}; 138};
149 139
@@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
151{ 141{
152 struct device_node *np; 142 struct device_node *np;
153 u32 val = 0x1; 143 u32 val = 0x1;
154 void __iomem *addr = EXYNOS_SWRESET; 144 void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
155 145
156 if (of_machine_is_compatible("samsung,exynos5440")) { 146 if (of_machine_is_compatible("samsung,exynos5440")) {
157 u32 status; 147 u32 status;
@@ -175,17 +165,6 @@ static struct platform_device exynos_cpuidle = {
175 .id = -1, 165 .id = -1,
176}; 166};
177 167
178void __init exynos_cpuidle_init(void)
179{
180 if (soc_is_exynos4210() || soc_is_exynos5250())
181 platform_device_register(&exynos_cpuidle);
182}
183
184void __init exynos_cpufreq_init(void)
185{
186 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
187}
188
189void __iomem *sysram_base_addr; 168void __iomem *sysram_base_addr;
190void __iomem *sysram_ns_base_addr; 169void __iomem *sysram_ns_base_addr;
191 170
@@ -335,8 +314,11 @@ static void __init exynos_dt_machine_init(void)
335 if (!IS_ENABLED(CONFIG_SMP)) 314 if (!IS_ENABLED(CONFIG_SMP))
336 exynos_sysram_init(); 315 exynos_sysram_init();
337 316
338 exynos_cpuidle_init(); 317 if (of_machine_is_compatible("samsung,exynos4210") ||
339 exynos_cpufreq_init(); 318 of_machine_is_compatible("samsung,exynos5250"))
319 platform_device_register(&exynos_cpuidle);
320
321 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
340 322
341 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 323 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
342} 324}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 963002fb15c3..f0b7e92bad6c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -27,9 +27,6 @@
27#define EXYNOS4_PA_SYSCON 0x10010000 27#define EXYNOS4_PA_SYSCON 0x10010000
28#define EXYNOS5_PA_SYSCON 0x10050100 28#define EXYNOS5_PA_SYSCON 0x10050100
29 29
30#define EXYNOS4_PA_PMU 0x10020000
31#define EXYNOS5_PA_PMU 0x10040000
32
33#define EXYNOS4_PA_CMU 0x10030000 30#define EXYNOS4_PA_CMU 0x10030000
34#define EXYNOS5_PA_CMU 0x10010000 31#define EXYNOS5_PA_CMU 0x10010000
35 32
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index a96b78f93f2b..b2f8b60cf0e9 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -26,6 +26,10 @@
26#define EXYNOS5420_CPUS_PER_CLUSTER 4 26#define EXYNOS5420_CPUS_PER_CLUSTER 4
27#define EXYNOS5420_NR_CLUSTERS 2 27#define EXYNOS5420_NR_CLUSTERS 2
28 28
29#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
30#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
31#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
32
29/* 33/*
30 * The common v7_exit_coherency_flush API could not be used because of the 34 * The common v7_exit_coherency_flush API could not be used because of the
31 * Erratum 799270 workaround. This macro is the same as the common one (in 35 * Erratum 799270 workaround. This macro is the same as the common one (in
@@ -51,7 +55,7 @@
51 "dsb\n\t" \ 55 "dsb\n\t" \
52 "ldmfd sp!, {fp, ip}" \ 56 "ldmfd sp!, {fp, ip}" \
53 : \ 57 : \
54 : "Ir" (S5P_INFORM0) \ 58 : "Ir" (pmu_base_addr + S5P_INFORM0) \
55 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 59 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
56 "r9", "r10", "lr", "memory") 60 "r9", "r10", "lr", "memory")
57 61
@@ -73,36 +77,9 @@ cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
73 77
74#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster) 78#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
75 79
76static int exynos_cluster_power_control(unsigned int cluster, int enable)
77{
78 unsigned int tries = 100;
79 unsigned int val;
80
81 if (enable) {
82 exynos_cluster_power_up(cluster);
83 val = S5P_CORE_LOCAL_PWR_EN;
84 } else {
85 exynos_cluster_power_down(cluster);
86 val = 0;
87 }
88
89 /* Wait until cluster power control is applied */
90 while (tries--) {
91 if (exynos_cluster_power_state(cluster) == val)
92 return 0;
93
94 cpu_relax();
95 }
96 pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
97 enable ? "on" : "off");
98
99 return -ETIMEDOUT;
100}
101
102static int exynos_power_up(unsigned int cpu, unsigned int cluster) 80static int exynos_power_up(unsigned int cpu, unsigned int cluster)
103{ 81{
104 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); 82 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
105 int err = 0;
106 83
107 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); 84 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
108 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || 85 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
@@ -126,12 +103,9 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
126 * cores. 103 * cores.
127 */ 104 */
128 if (was_cluster_down) 105 if (was_cluster_down)
129 err = exynos_cluster_power_control(cluster, 1); 106 exynos_cluster_power_up(cluster);
130 107
131 if (!err) 108 exynos_cpu_power_up(cpunr);
132 exynos_cpu_power_up(cpunr);
133 else
134 exynos_cluster_power_control(cluster, 0);
135 } else if (cpu_use_count[cpu][cluster] != 2) { 109 } else if (cpu_use_count[cpu][cluster] != 2) {
136 /* 110 /*
137 * The only possible values are: 111 * The only possible values are:
@@ -147,7 +121,7 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
147 arch_spin_unlock(&exynos_mcpm_lock); 121 arch_spin_unlock(&exynos_mcpm_lock);
148 local_irq_enable(); 122 local_irq_enable();
149 123
150 return err; 124 return 0;
151} 125}
152 126
153/* 127/*
@@ -178,9 +152,10 @@ static void exynos_power_down(void)
178 if (cpu_use_count[cpu][cluster] == 0) { 152 if (cpu_use_count[cpu][cluster] == 0) {
179 exynos_cpu_power_down(cpunr); 153 exynos_cpu_power_down(cpunr);
180 154
181 if (exynos_cluster_unused(cluster)) 155 if (exynos_cluster_unused(cluster)) {
182 /* TODO: Turn off the cluster here to save power. */ 156 exynos_cluster_power_down(cluster);
183 last_man = true; 157 last_man = true;
158 }
184 } else if (cpu_use_count[cpu][cluster] == 1) { 159 } else if (cpu_use_count[cpu][cluster] == 1) {
185 /* 160 /*
186 * A power_up request went ahead of us. 161 * A power_up request went ahead of us.
@@ -257,10 +232,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
257 return -ETIMEDOUT; /* timeout */ 232 return -ETIMEDOUT; /* timeout */
258} 233}
259 234
235static void exynos_powered_up(void)
236{
237 unsigned int mpidr, cpu, cluster;
238
239 mpidr = read_cpuid_mpidr();
240 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
241 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
242
243 arch_spin_lock(&exynos_mcpm_lock);
244 if (cpu_use_count[cpu][cluster] == 0)
245 cpu_use_count[cpu][cluster] = 1;
246 arch_spin_unlock(&exynos_mcpm_lock);
247}
248
249static void exynos_suspend(u64 residency)
250{
251 unsigned int mpidr, cpunr;
252
253 exynos_power_down();
254
255 /*
256 * Execution reaches here only if cpu did not power down.
257 * Hence roll back the changes done in exynos_power_down function.
258 *
259 * CAUTION: "This function requires the stack data to be visible through
260 * power down and can only be executed on processors like A15 and A7
261 * that hit the cache with the C bit clear in the SCTLR register."
262 */
263 mpidr = read_cpuid_mpidr();
264 cpunr = exynos_pmu_cpunr(mpidr);
265
266 exynos_cpu_power_up(cpunr);
267}
268
260static const struct mcpm_platform_ops exynos_power_ops = { 269static const struct mcpm_platform_ops exynos_power_ops = {
261 .power_up = exynos_power_up, 270 .power_up = exynos_power_up,
262 .power_down = exynos_power_down, 271 .power_down = exynos_power_down,
263 .wait_for_powerdown = exynos_wait_for_powerdown, 272 .wait_for_powerdown = exynos_wait_for_powerdown,
273 .suspend = exynos_suspend,
274 .powered_up = exynos_powered_up,
264}; 275};
265 276
266static void __init exynos_mcpm_usage_count_init(void) 277static void __init exynos_mcpm_usage_count_init(void)
@@ -312,6 +323,7 @@ static int __init exynos_mcpm_init(void)
312{ 323{
313 struct device_node *node; 324 struct device_node *node;
314 void __iomem *ns_sram_base_addr; 325 void __iomem *ns_sram_base_addr;
326 unsigned int value, i;
315 int ret; 327 int ret;
316 328
317 node = of_find_matching_node(NULL, exynos_dt_mcpm_match); 329 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
@@ -338,7 +350,7 @@ static int __init exynos_mcpm_init(void)
338 * To increase the stability of KFC reset we need to program 350 * To increase the stability of KFC reset we need to program
339 * the PMU SPARE3 register 351 * the PMU SPARE3 register
340 */ 352 */
341 __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); 353 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
342 354
343 exynos_mcpm_usage_count_init(); 355 exynos_mcpm_usage_count_init();
344 356
@@ -357,6 +369,26 @@ static int __init exynos_mcpm_init(void)
357 pr_info("Exynos MCPM support installed\n"); 369 pr_info("Exynos MCPM support installed\n");
358 370
359 /* 371 /*
372 * On Exynos5420/5800 for the A15 and A7 clusters:
373 *
374 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
375 * in a cluster are turned off before turning off the cluster L2.
376 *
377 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
378 * off before waking it up.
379 *
380 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
381 * turned on before the first man is powered up.
382 */
383 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
384 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
385 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
386 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
387 EXYNOS5420_USE_L2_COMMON_UP_STATE;
388 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
389 }
390
391 /*
360 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr 392 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
361 * as part of secondary_cpu_start(). Let's redirect it to the 393 * as part of secondary_cpu_start(). Let's redirect it to the
362 * mcpm_entry_point(). 394 * mcpm_entry_point().
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index e5a8d764f24c..a9f1cf759949 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,6 +26,8 @@
26#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
27#include <asm/firmware.h> 27#include <asm/firmware.h>
28 28
29#include <mach/map.h>
30
29#include "common.h" 31#include "common.h"
30#include "regs-pmu.h" 32#include "regs-pmu.h"
31 33
@@ -41,7 +43,7 @@ extern void exynos4_secondary_startup(void);
41 */ 43 */
42void exynos_cpu_power_down(int cpu) 44void exynos_cpu_power_down(int cpu)
43{ 45{
44 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 46 pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
45} 47}
46 48
47/** 49/**
@@ -52,8 +54,8 @@ void exynos_cpu_power_down(int cpu)
52 */ 54 */
53void exynos_cpu_power_up(int cpu) 55void exynos_cpu_power_up(int cpu)
54{ 56{
55 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 57 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
56 EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 58 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
57} 59}
58 60
59/** 61/**
@@ -63,7 +65,7 @@ void exynos_cpu_power_up(int cpu)
63 */ 65 */
64int exynos_cpu_power_state(int cpu) 66int exynos_cpu_power_state(int cpu)
65{ 67{
66 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 68 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
67 S5P_CORE_LOCAL_PWR_EN); 69 S5P_CORE_LOCAL_PWR_EN);
68} 70}
69 71
@@ -73,7 +75,7 @@ int exynos_cpu_power_state(int cpu)
73 */ 75 */
74void exynos_cluster_power_down(int cluster) 76void exynos_cluster_power_down(int cluster)
75{ 77{
76 __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 78 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
77} 79}
78 80
79/** 81/**
@@ -82,8 +84,8 @@ void exynos_cluster_power_down(int cluster)
82 */ 84 */
83void exynos_cluster_power_up(int cluster) 85void exynos_cluster_power_up(int cluster)
84{ 86{
85 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 87 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
86 EXYNOS_COMMON_CONFIGURATION(cluster)); 88 EXYNOS_COMMON_CONFIGURATION(cluster));
87} 89}
88 90
89/** 91/**
@@ -93,14 +95,14 @@ void exynos_cluster_power_up(int cluster)
93 */ 95 */
94int exynos_cluster_power_state(int cluster) 96int exynos_cluster_power_state(int cluster)
95{ 97{
96 return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 98 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
97 S5P_CORE_LOCAL_PWR_EN); 99 S5P_CORE_LOCAL_PWR_EN);
98} 100}
99 101
100static inline void __iomem *cpu_boot_reg_base(void) 102static inline void __iomem *cpu_boot_reg_base(void)
101{ 103{
102 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 104 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
103 return S5P_INFORM5; 105 return pmu_base_addr + S5P_INFORM5;
104 return sysram_base_addr; 106 return sysram_base_addr;
105} 107}
106 108
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 6ab68a068e93..18646b7e226b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -28,7 +28,6 @@
28#include <asm/suspend.h> 28#include <asm/suspend.h>
29 29
30#include <plat/pm-common.h> 30#include <plat/pm-common.h>
31#include <plat/pll.h>
32#include <plat/regs-srom.h> 31#include <plat/regs-srom.h>
33 32
34#include <mach/map.h> 33#include <mach/map.h>
@@ -102,11 +101,15 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
102} 101}
103 102
104#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 103#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
105 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 104 pmu_base_addr + S5P_INFORM7 : \
106 (sysram_base_addr + 0x24) : S5P_INFORM0)) 105 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
106 (sysram_base_addr + 0x24) : \
107 pmu_base_addr + S5P_INFORM0))
107#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 108#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
108 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 109 pmu_base_addr + S5P_INFORM6 : \
109 (sysram_base_addr + 0x20) : S5P_INFORM1)) 110 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
111 (sysram_base_addr + 0x20) : \
112 pmu_base_addr + S5P_INFORM1))
110 113
111#define S5P_CHECK_AFTR 0xFCBA0D10 114#define S5P_CHECK_AFTR 0xFCBA0D10
112#define S5P_CHECK_SLEEP 0x00000BAD 115#define S5P_CHECK_SLEEP 0x00000BAD
@@ -114,7 +117,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
114/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 117/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
115static void exynos_set_wakeupmask(long mask) 118static void exynos_set_wakeupmask(long mask)
116{ 119{
117 __raw_writel(mask, S5P_WAKEUP_MASK); 120 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
118} 121}
119 122
120static void exynos_cpu_set_boot_vector(long flags) 123static void exynos_cpu_set_boot_vector(long flags)
@@ -191,27 +194,27 @@ static void exynos_pm_prepare(void)
191 unsigned int tmp; 194 unsigned int tmp;
192 195
193 /* Set wake-up mask registers */ 196 /* Set wake-up mask registers */
194 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 197 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
195 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 198 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
196 199
197 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 200 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
198 201
199 if (soc_is_exynos5250()) { 202 if (soc_is_exynos5250()) {
200 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 203 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
201 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 204 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
202 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 205 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
203 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 206 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
204 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 207 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
205 } 208 }
206 209
207 /* Set value of power down register for sleep mode */ 210 /* Set value of power down register for sleep mode */
208 211
209 exynos_sys_powerdown_conf(SYS_SLEEP); 212 exynos_sys_powerdown_conf(SYS_SLEEP);
210 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 213 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
211 214
212 /* ensure at least INFORM0 has the resume address */ 215 /* ensure at least INFORM0 has the resume address */
213 216
214 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 217 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
215} 218}
216 219
217static void exynos_pm_central_suspend(void) 220static void exynos_pm_central_suspend(void)
@@ -219,9 +222,9 @@ static void exynos_pm_central_suspend(void)
219 unsigned long tmp; 222 unsigned long tmp;
220 223
221 /* Setting Central Sequence Register for power down mode */ 224 /* Setting Central Sequence Register for power down mode */
222 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 225 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
223 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 226 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
224 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 227 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
225} 228}
226 229
227static int exynos_pm_suspend(void) 230static int exynos_pm_suspend(void)
@@ -233,7 +236,7 @@ static int exynos_pm_suspend(void)
233 /* Setting SEQ_OPTION register */ 236 /* Setting SEQ_OPTION register */
234 237
235 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 238 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
236 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 239 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
237 240
238 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 241 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
239 exynos_cpu_save_register(); 242 exynos_cpu_save_register();
@@ -251,12 +254,12 @@ static int exynos_pm_central_resume(void)
251 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 254 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
252 * in this situation. 255 * in this situation.
253 */ 256 */
254 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 257 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
255 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 258 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
256 tmp |= S5P_CENTRAL_LOWPWR_CFG; 259 tmp |= S5P_CENTRAL_LOWPWR_CFG;
257 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 260 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
258 /* clear the wakeup state register */ 261 /* clear the wakeup state register */
259 __raw_writel(0x0, S5P_WAKEUP_STAT); 262 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
260 /* No need to perform below restore code */ 263 /* No need to perform below restore code */
261 return -1; 264 return -1;
262 } 265 }
@@ -274,13 +277,13 @@ static void exynos_pm_resume(void)
274 277
275 /* For release retention */ 278 /* For release retention */
276 279
277 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 280 pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
278 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 281 pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
279 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 282 pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
280 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 283 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
281 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 284 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
282 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 285 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
283 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 286 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
284 287
285 if (soc_is_exynos5250()) 288 if (soc_is_exynos5250())
286 s3c_pm_do_restore(exynos5_sys_save, 289 s3c_pm_do_restore(exynos5_sys_save,
@@ -294,7 +297,7 @@ static void exynos_pm_resume(void)
294early_wakeup: 297early_wakeup:
295 298
296 /* Clear SLEEP mode set in INFORM1 */ 299 /* Clear SLEEP mode set in INFORM1 */
297 __raw_writel(0x0, S5P_INFORM1); 300 pmu_raw_writel(0x0, S5P_INFORM1);
298 301
299 return; 302 return;
300} 303}
@@ -338,7 +341,7 @@ static int exynos_suspend_enter(suspend_state_t state)
338 s3c_pm_restore_uarts(); 341 s3c_pm_restore_uarts();
339 342
340 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 343 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
341 __raw_readl(S5P_WAKEUP_STAT)); 344 pmu_raw_readl(S5P_WAKEUP_STAT));
342 345
343 s3c_pm_check_restore(); 346 s3c_pm_check_restore();
344 347
@@ -408,9 +411,9 @@ void __init exynos_pm_init(void)
408 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 411 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
409 412
410 /* All wakeup disable */ 413 /* All wakeup disable */
411 tmp = __raw_readl(S5P_WAKEUP_MASK); 414 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
412 tmp |= ((0xFF << 8) | (0x1F << 1)); 415 tmp |= ((0xFF << 8) | (0x1F << 1));
413 __raw_writel(tmp, S5P_WAKEUP_MASK); 416 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
414 417
415 register_syscore_ops(&exynos_pm_syscore_ops); 418 register_syscore_ops(&exynos_pm_syscore_ops);
416 suspend_set_ops(&exynos_suspend_ops); 419 suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index dcfcb44c3c55..ff9d23f0a7d9 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -18,7 +18,7 @@
18static const struct exynos_pmu_conf *exynos_pmu_config; 18static const struct exynos_pmu_conf *exynos_pmu_config;
19 19
20static const struct exynos_pmu_conf exynos4210_pmu_config[] = { 20static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
21 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 21 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
212}; 212};
213 213
214static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 214static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
215 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 215 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
315 { PMU_TABLE_END,}, 315 { PMU_TABLE_END,},
316}; 316};
317 317
318static void __iomem * const exynos5_list_both_cnt_feed[] = { 318static unsigned int const exynos5_list_both_cnt_feed[] = {
319 EXYNOS5_ARM_CORE0_OPTION, 319 EXYNOS5_ARM_CORE0_OPTION,
320 EXYNOS5_ARM_CORE1_OPTION, 320 EXYNOS5_ARM_CORE1_OPTION,
321 EXYNOS5_ARM_COMMON_OPTION, 321 EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
329 EXYNOS5_TOP_PWR_SYSMEM_OPTION, 329 EXYNOS5_TOP_PWR_SYSMEM_OPTION,
330}; 330};
331 331
332static void __iomem * const exynos5_list_diable_wfi_wfe[] = { 332static unsigned int const exynos5_list_diable_wfi_wfe[] = {
333 EXYNOS5_ARM_CORE1_OPTION, 333 EXYNOS5_ARM_CORE1_OPTION,
334 EXYNOS5_FSYS_ARM_OPTION, 334 EXYNOS5_FSYS_ARM_OPTION,
335 EXYNOS5_ISP_ARM_OPTION, 335 EXYNOS5_ISP_ARM_OPTION,
@@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
344 * Enable both SC_FEEDBACK and SC_COUNTER 344 * Enable both SC_FEEDBACK and SC_COUNTER
345 */ 345 */
346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) { 346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
347 tmp = __raw_readl(exynos5_list_both_cnt_feed[i]); 347 tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
348 tmp |= (EXYNOS5_USE_SC_FEEDBACK | 348 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
349 EXYNOS5_USE_SC_COUNTER); 349 EXYNOS5_USE_SC_COUNTER);
350 __raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 350 pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
351 } 351 }
352 352
353 /* 353 /*
354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
355 */ 355 */
356 tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); 356 tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
358 __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 358 pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
359 359
360 /* 360 /*
361 * Disable WFI/WFE on XXX_OPTION 361 * Disable WFI/WFE on XXX_OPTION
362 */ 362 */
363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) { 363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
364 tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]); 364 tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
366 EXYNOS5_OPTION_USE_STANDBYWFI); 366 EXYNOS5_OPTION_USE_STANDBYWFI);
367 __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]); 367 pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
368 } 368 }
369} 369}
370 370
@@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
375 if (soc_is_exynos5250()) 375 if (soc_is_exynos5250())
376 exynos5_init_pmu(); 376 exynos5_init_pmu();
377 377
378 for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++) 378 for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
379 __raw_writel(exynos_pmu_config[i].val[mode], 379 pmu_raw_writel(exynos_pmu_config[i].val[mode],
380 exynos_pmu_config[i].reg); 380 exynos_pmu_config[i].offset);
381 381
382 if (soc_is_exynos4412()) { 382 if (soc_is_exynos4412()) {
383 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) 383 for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
384 __raw_writel(exynos4412_pmu_config[i].val[mode], 384 pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
385 exynos4412_pmu_config[i].reg); 385 exynos4412_pmu_config[i].offset);
386 } 386 }
387} 387}
388 388
@@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
403 * When SYS_WDTRESET is set, watchdog timer reset request 403 * When SYS_WDTRESET is set, watchdog timer reset request
404 * is ignored by power management unit. 404 * is ignored by power management unit.
405 */ 405 */
406 value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 406 value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
407 value &= ~EXYNOS5_SYS_WDTRESET; 407 value &= ~EXYNOS5_SYS_WDTRESET;
408 __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 408 pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
409 409
410 value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 410 value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
411 value &= ~EXYNOS5_SYS_WDTRESET; 411 value &= ~EXYNOS5_SYS_WDTRESET;
412 __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 412 pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
413 413
414 exynos_pmu_config = exynos5250_pmu_config; 414 exynos_pmu_config = exynos5250_pmu_config;
415 pr_info("EXYNOS5250 PMU Initialize\n"); 415 pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1993e6bd5388..96a1569262b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,300 +12,298 @@
12#ifndef __ASM_ARCH_REGS_PMU_H 12#ifndef __ASM_ARCH_REGS_PMU_H
13#define __ASM_ARCH_REGS_PMU_H __FILE__ 13#define __ASM_ARCH_REGS_PMU_H __FILE__
14 14
15#include <mach/map.h> 15#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
16
17#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
18
19#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
20 16
21#define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 17#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
22 18
23#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) 19#define S5P_CENTRAL_SEQ_OPTION 0x0208
24 20
25#define S5P_USE_STANDBY_WFI0 (1 << 16) 21#define S5P_USE_STANDBY_WFI0 (1 << 16)
26#define S5P_USE_STANDBY_WFE0 (1 << 24) 22#define S5P_USE_STANDBY_WFE0 (1 << 24)
27 23
28#define EXYNOS_SWRESET S5P_PMUREG(0x0400) 24#define EXYNOS_SWRESET 0x0400
29#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) 25#define EXYNOS5440_SWRESET 0x00C4
30 26
31#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 27#define S5P_WAKEUP_STAT 0x0600
32#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 28#define S5P_EINT_WAKEUP_MASK 0x0604
33#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 29#define S5P_WAKEUP_MASK 0x0608
34 30
35#define S5P_INFORM0 S5P_PMUREG(0x0800) 31#define S5P_INFORM0 0x0800
36#define S5P_INFORM1 S5P_PMUREG(0x0804) 32#define S5P_INFORM1 0x0804
37#define S5P_INFORM5 S5P_PMUREG(0x0814) 33#define S5P_INFORM5 0x0814
38#define S5P_INFORM6 S5P_PMUREG(0x0818) 34#define S5P_INFORM6 0x0818
39#define S5P_INFORM7 S5P_PMUREG(0x081C) 35#define S5P_INFORM7 0x081C
40#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C) 36#define S5P_PMU_SPARE3 0x090C
41 37
42#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) 38#define S5P_ARM_CORE0_LOWPWR 0x1000
43#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) 39#define S5P_DIS_IRQ_CORE0 0x1004
44#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) 40#define S5P_DIS_IRQ_CENTRAL0 0x1008
45#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) 41#define S5P_ARM_CORE1_LOWPWR 0x1010
46#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) 42#define S5P_DIS_IRQ_CORE1 0x1014
47#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) 43#define S5P_DIS_IRQ_CENTRAL1 0x1018
48#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) 44#define S5P_ARM_COMMON_LOWPWR 0x1080
49#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) 45#define S5P_L2_0_LOWPWR 0x10C0
50#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) 46#define S5P_L2_1_LOWPWR 0x10C4
51#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) 47#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
52#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) 48#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
53#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) 49#define S5P_CMU_RESET_LOWPWR 0x110C
54#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) 50#define S5P_APLL_SYSCLK_LOWPWR 0x1120
55#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) 51#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
56#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) 52#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
57#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) 53#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
58#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) 54#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
59#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) 55#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
60#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) 56#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
61#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) 57#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
62#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 58#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
63#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 59#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
64#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 60#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
65#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 61#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
66#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 62#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
67#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 63#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
68#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) 64#define S5P_CMU_RESET_TV_LOWPWR 0x1164
69#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 65#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
70#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 66#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
71#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 67#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
72#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 68#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
73#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 69#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
74#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 70#define S5P_TOP_BUS_LOWPWR 0x1180
75#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) 71#define S5P_TOP_RETENTION_LOWPWR 0x1184
76#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 72#define S5P_TOP_PWR_LOWPWR 0x1188
77#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 73#define S5P_LOGIC_RESET_LOWPWR 0x11A0
78#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 74#define S5P_ONENAND_MEM_LOWPWR 0x11C0
79#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 75#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
80#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 76#define S5P_USBOTG_MEM_LOWPWR 0x11CC
81#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 77#define S5P_HSMMC_MEM_LOWPWR 0x11D0
82#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 78#define S5P_CSSYS_MEM_LOWPWR 0x11D4
83#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 79#define S5P_SECSS_MEM_LOWPWR 0x11D8
84#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 80#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
85#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 81#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
86#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 82#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
87#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) 83#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
88#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) 84#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
89#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) 85#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
90#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) 86#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
91#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) 87#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
92#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) 88#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
93#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) 89#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
94#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) 90#define S5P_XUSBXTI_LOWPWR 0x1280
95#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) 91#define S5P_XXTI_LOWPWR 0x1284
96#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) 92#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
97#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) 93#define S5P_GPIO_MODE_LOWPWR 0x1300
98#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) 94#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
99#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) 95#define S5P_CAM_LOWPWR 0x1380
100#define S5P_TV_LOWPWR S5P_PMUREG(0x1384) 96#define S5P_TV_LOWPWR 0x1384
101#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 97#define S5P_MFC_LOWPWR 0x1388
102#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 98#define S5P_G3D_LOWPWR 0x138C
103#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 99#define S5P_LCD0_LOWPWR 0x1390
104#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 100#define S5P_MAUDIO_LOWPWR 0x1398
105#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 101#define S5P_GPS_LOWPWR 0x139C
106#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 102#define S5P_GPS_ALIVE_LOWPWR 0x13A0
107 103
108#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) 104#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
109#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 105#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
110 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 106 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
111#define EXYNOS_ARM_CORE_STATUS(_nr) \ 107#define EXYNOS_ARM_CORE_STATUS(_nr) \
112 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 108 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
113 109
114#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500) 110#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
115#define EXYNOS_COMMON_CONFIGURATION(_nr) \ 111#define EXYNOS_COMMON_CONFIGURATION(_nr) \
116 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 112 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
117#define EXYNOS_COMMON_STATUS(_nr) \ 113#define EXYNOS_COMMON_STATUS(_nr) \
118 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 114 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
115#define EXYNOS_COMMON_OPTION(_nr) \
116 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
119 117
120#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) 118#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
121#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) 119#define S5P_PAD_RET_GPIO_OPTION 0x3108
122#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) 120#define S5P_PAD_RET_UART_OPTION 0x3128
123#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) 121#define S5P_PAD_RET_MMCA_OPTION 0x3148
124#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) 122#define S5P_PAD_RET_MMCB_OPTION 0x3168
125#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) 123#define S5P_PAD_RET_EBIA_OPTION 0x3188
126#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) 124#define S5P_PAD_RET_EBIB_OPTION 0x31A8
127 125
128#define S5P_CORE_LOCAL_PWR_EN 0x3 126#define S5P_CORE_LOCAL_PWR_EN 0x3
129 127
130/* Only for EXYNOS4210 */ 128/* Only for EXYNOS4210 */
131#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) 129#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
132#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) 130#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
133#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) 131#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
134#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) 132#define S5P_PCIE_MEM_LOWPWR 0x11E0
135#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) 133#define S5P_SATA_MEM_LOWPWR 0x11E4
136#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) 134#define S5P_LCD1_LOWPWR 0x1394
137 135
138/* Only for EXYNOS4x12 */ 136/* Only for EXYNOS4x12 */
139#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 137#define S5P_ISP_ARM_LOWPWR 0x1050
140#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 138#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
141#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 139#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
142#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) 140#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
143#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) 141#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
144#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) 142#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
145#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) 143#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
146#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) 144#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
147#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) 145#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
148#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) 146#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
149#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) 147#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
150#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) 148#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
151#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) 149#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
152#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) 150#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
153#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) 151#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
154#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) 152#define S5P_HSI_MEM_LOWPWR 0x11C4
155#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) 153#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
156#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) 154#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
157#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) 155#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
158#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) 156#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
159#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) 157#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
160#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) 158#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
161#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) 159#define S5P_ISP_LOWPWR 0x1394
162#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) 160#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
163#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) 161#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
164#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) 162#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
165#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) 163#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
166#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) 164#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
167 165
168#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) 166#define S5P_ARM_L2_0_OPTION 0x2608
169#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) 167#define S5P_ARM_L2_1_OPTION 0x2628
170#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) 168#define S5P_ONENAND_MEM_OPTION 0x2E08
171#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) 169#define S5P_HSI_MEM_OPTION 0x2E28
172#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) 170#define S5P_G2D_ACP_MEM_OPTION 0x2E48
173#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) 171#define S5P_USBOTG_MEM_OPTION 0x2E68
174#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) 172#define S5P_HSMMC_MEM_OPTION 0x2E88
175#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) 173#define S5P_CSSYS_MEM_OPTION 0x2EA8
176#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 174#define S5P_SECSS_MEM_OPTION 0x2EC8
177#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 175#define S5P_ROTATOR_MEM_OPTION 0x2F48
178 176
179/* Only for EXYNOS4412 */ 177/* Only for EXYNOS4412 */
180#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) 178#define S5P_ARM_CORE2_LOWPWR 0x1020
181#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) 179#define S5P_DIS_IRQ_CORE2 0x1024
182#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) 180#define S5P_DIS_IRQ_CENTRAL2 0x1028
183#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) 181#define S5P_ARM_CORE3_LOWPWR 0x1030
184#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) 182#define S5P_DIS_IRQ_CORE3 0x1034
185#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) 183#define S5P_DIS_IRQ_CENTRAL3 0x1038
186 184
187/* For EXYNOS5 */ 185/* For EXYNOS5 */
188 186
189#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) 187#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
190#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) 188#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
191 189
192#define EXYNOS5_SYS_WDTRESET (1 << 20) 190#define EXYNOS5_SYS_WDTRESET (1 << 20)
193 191
194#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) 192#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
195#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) 193#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
196#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) 194#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
197#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010) 195#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
198#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014) 196#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
199#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018) 197#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
200#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040) 198#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
201#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048) 199#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
202#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050) 200#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
203#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054) 201#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
204#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058) 202#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
205#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080) 203#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
206#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0) 204#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
207#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100) 205#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
208#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104) 206#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
209#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C) 207#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
210#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120) 208#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
211#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124) 209#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
212#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C) 210#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
213#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130) 211#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
214#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134) 212#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
215#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138) 213#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
216#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140) 214#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
217#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144) 215#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
218#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148) 216#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
219#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C) 217#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
220#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150) 218#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
221#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154) 219#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
222#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164) 220#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
223#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170) 221#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
224#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180) 222#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
225#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184) 223#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
226#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188) 224#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
227#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190) 225#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
228#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194) 226#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
229#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198) 227#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
230#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0) 228#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
231#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4) 229#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
232#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0) 230#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
233#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4) 231#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
234#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0) 232#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
235#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8) 233#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
236#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC) 234#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
237#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0) 235#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
238#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4) 236#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
239#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8) 237#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
240#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC) 238#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
241#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0) 239#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
242#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4) 240#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
243#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8) 241#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
244#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC) 242#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
245#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4) 243#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
246#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC) 244#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
247#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200) 245#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
248#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204) 246#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
249#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208) 247#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
250#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) 248#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
251#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224) 249#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
252#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228) 250#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
253#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C) 251#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
254#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230) 252#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
255#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234) 253#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
256#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238) 254#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
257#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C) 255#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
258#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240) 256#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
259#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250) 257#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
260#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260) 258#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
261#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280) 259#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
262#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284) 260#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
263#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0) 261#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
264#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300) 262#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
265#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320) 263#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
266#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340) 264#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
267#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344) 265#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
268#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348) 266#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
269#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400) 267#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
270#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404) 268#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
271#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408) 269#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
272#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C) 270#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
273#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) 271#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
274#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418) 272#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
275#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480) 273#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
276#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484) 274#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
277#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488) 275#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
278#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C) 276#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
279#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494) 277#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
280#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498) 278#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
281#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0) 279#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
282#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4) 280#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
283#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8) 281#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
284#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC) 282#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
285#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4) 283#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
286#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8) 284#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
287#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580) 285#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
288#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584) 286#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
289#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588) 287#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
290#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C) 288#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
291#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594) 289#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
292#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598) 290#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
293 291
294#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008) 292#define EXYNOS5_ARM_CORE0_OPTION 0x2008
295#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088) 293#define EXYNOS5_ARM_CORE1_OPTION 0x2088
296#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) 294#define EXYNOS5_FSYS_ARM_OPTION 0x2208
297#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) 295#define EXYNOS5_ISP_ARM_OPTION 0x2288
298#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) 296#define EXYNOS5_ARM_COMMON_OPTION 0x2408
299#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) 297#define EXYNOS5_ARM_L2_OPTION 0x2608
300#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) 298#define EXYNOS5_TOP_PWR_OPTION 0x2C48
301#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) 299#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
302#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) 300#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
303#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) 301#define EXYNOS5_GSCL_OPTION 0x4008
304#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) 302#define EXYNOS5_ISP_OPTION 0x4028
305#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) 303#define EXYNOS5_MFC_OPTION 0x4048
306#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) 304#define EXYNOS5_G3D_OPTION 0x4068
307#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) 305#define EXYNOS5_DISP1_OPTION 0x40A8
308#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) 306#define EXYNOS5_MAU_OPTION 0x40C8
309 307
310#define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 308#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
311#define EXYNOS5_USE_SC_COUNTER (1 << 0) 309#define EXYNOS5_USE_SC_COUNTER (1 << 0)
@@ -319,4 +317,13 @@
319 317
320#define EXYNOS5420_SWRESET_KFC_SEL 0x3 318#define EXYNOS5420_SWRESET_KFC_SEL 0x3
321 319
320#include <asm/cputype.h>
321#define MAX_CPUS_IN_CLUSTER 4
322
323static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
324{
325 return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
326 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
327}
328
322#endif /* __ASM_ARCH_REGS_PMU_H */ 329#endif /* __ASM_ARCH_REGS_PMU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 13:23:06 -0500