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authorMarc Zyngier <marc.zyngier@arm.com>2011-11-12 11:09:49 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2011-11-15 13:13:03 -0500
commitdb0d4db22a78d31c59087f7057b8f1612fecc35d (patch)
treee2d84ee2c816d4bef066806863a3937792a08581 /arch/arm/mach-exynos
parentcfcfc9eca2bcbd26a8e206baeb005b055dbf8e37 (diff)
ARM: gic: allow GIC to support non-banked setups
The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/cpu.c16
-rw-r--r--arch/arm/mach-exynos/platsmp.c28
2 files changed, 2 insertions, 42 deletions
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index 90ec247f3b37..e92e464bdbba 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -207,27 +207,13 @@ void __init exynos4_init_clocks(int xtal)
207 exynos4_setup_clocks(); 207 exynos4_setup_clocks();
208} 208}
209 209
210static void exynos4_gic_irq_fix_base(struct irq_data *d)
211{
212 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
213
214 gic_data->cpu_base = S5P_VA_GIC_CPU +
215 (gic_bank_offset * smp_processor_id());
216
217 gic_data->dist_base = S5P_VA_GIC_DIST +
218 (gic_bank_offset * smp_processor_id());
219}
220
221void __init exynos4_init_irq(void) 210void __init exynos4_init_irq(void)
222{ 211{
223 int irq; 212 int irq;
224 213
225 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 214 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226 215
227 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 216 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
228 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
231 217
232 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 218 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
233 219
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb3875..60bc45e3e709 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,7 +32,6 @@
32 32
33#include <plat/cpu.h> 33#include <plat/cpu.h>
34 34
35extern unsigned int gic_bank_offset;
36extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
37 36
38#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +64,6 @@ static void __iomem *scu_base_addr(void)
65 64
66static DEFINE_SPINLOCK(boot_lock); 65static DEFINE_SPINLOCK(boot_lock);
67 66
68static void __cpuinit exynos4_gic_secondary_init(void)
69{
70 void __iomem *dist_base = S5P_VA_GIC_DIST +
71 (gic_bank_offset * smp_processor_id());
72 void __iomem *cpu_base = S5P_VA_GIC_CPU +
73 (gic_bank_offset * smp_processor_id());
74 int i;
75
76 /*
77 * Deal with the banked PPI and SGI interrupts - disable all
78 * PPI interrupts, ensure all SGI interrupts are enabled.
79 */
80 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
81 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
82
83 /*
84 * Set priority on PPI and SGI interrupts
85 */
86 for (i = 0; i < 32; i += 4)
87 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
88
89 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
90 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
91}
92
93void __cpuinit platform_secondary_init(unsigned int cpu) 67void __cpuinit platform_secondary_init(unsigned int cpu)
94{ 68{
95 /* 69 /*
@@ -97,7 +71,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
97 * core (e.g. timer irq), then they will not have been enabled 71 * core (e.g. timer irq), then they will not have been enabled
98 * for us: do so 72 * for us: do so
99 */ 73 */
100 exynos4_gic_secondary_init(); 74 gic_secondary_init(0);
101 75
102 /* 76 /*
103 * let the primary processor know we're out of the 77 * let the primary processor know we're out of the