Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM Soc updates, take 2, from Olof Johansson:
 "This is the second batch of SoC updates for the 3.8 merge window,
  containing parts that had dependencies on earlier branches such that
  we couldn't include them with the first branch.

  These are general updates for Samsung Exynos, Renesas/shmobile and a
  topic branch that adds SMP support to Altera's socfpga platform."

Fix up conflicts mostly as per Olof.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: EXYNOS: Clock settings for SATA and SATA PHY
  ARM: EXYNOS: Add ARM down clock support
  ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
  ARM: EXYNOS: Add aliases for i2c controller
  ARM: EXYNOS: Setup legacy i2c controller interrupts
  sh: clkfwk: fixup unsed variable warning
  Revert "ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode"
  Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
  Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode"
  ARM: highbank: use common debug_ll_io_init
  ARM: shmobile: sh7372: sh7372_fsiXck_clk become non-global
  ARM: shmobile: sh7372: remove fsidivx clock
  ARM: socfpga: mark secondary_trampoline as cpuinit
  socfpga: map uart into virtual address space so that early_printk() works
  ARM: socfpga: fix build break for allyesconfig
  ARM: socfpga: Enable SMP for socfpga
  ARM: EXYNOS: Add dp clock support for EXYNOS5
  ARM: SAMSUNG: call clk_get_rate for debugfs rate files
  ARM: SAMSUNG: add clock_tree debugfs file in clock

6 files changed, 116 insertions, 4 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 7652f5d78a56..e9d7b80bae49 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -80,6 +80,8 @@ static struct sleep_save exynos5_clock_save[] = {
         SAVE_ITEM(EXYNOS5_VPLL_CON0),
         SAVE_ITEM(EXYNOS5_VPLL_CON1),
         SAVE_ITEM(EXYNOS5_VPLL_CON2),
+        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
 };
 #endif
 
@@ -661,15 +663,20 @@ static struct clk exynos5_init_clocks_off[] = {
                 .ctrlbit        = (1 << 15),
         }, {
                 .name           = "sata",
-                .devname        = "ahci",
+                .devname        = "exynos5-sata",
+                .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
-                .name           = "sata_phy",
+                .name           = "sata-phy",
+                .devname        = "exynos5-sata-phy",
+                .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 24),
         }, {
-                .name           = "sata_phy_i2c",
+                .name           = "i2c",
+                .devname        = "exynos5-sata-phy-i2c",
+                .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 25),
         }, {
@@ -693,6 +700,11 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_disp1_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
+                .name           = "dp",
+                .devname        = "exynos-dp",
+                .enable         = exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                 .name           = "jpeg",
                 .enable         = exynos5_clk_ip_gen_ctrl,
                 .ctrlbit        = (1 << 2),
@@ -1241,6 +1253,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
         }, {
                 .clk    = {
+                        .name           = "sclk_sata",
+                        .devname        = "exynos5-sata",
+                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos5_clkset_aclk,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
                         .name           = "sclk_gscl_wrap",
                         .devname        = "s5p-mipi-csis.0",
                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 8e4ec21ef2cf..050924152776 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -21,6 +21,7 @@
 #include <asm/suspend.h>
 #include <asm/unified.h>
 #include <asm/cpuidle.h>
+#include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pmu.h>
 
@@ -157,12 +158,47 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                 return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
 
+static void __init exynos5_core_down_clk(void)
+{
+        unsigned int tmp;
+
+        /*
+         * Enable arm clock down (in idle) and set arm divider
+         * ratios in WFI/WFE state.
+         */
+        tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
+              PWR_CTRL1_CORE1_DOWN_RATIO | \
+              PWR_CTRL1_DIV2_DOWN_EN     | \
+              PWR_CTRL1_DIV1_DOWN_EN     | \
+              PWR_CTRL1_USE_CORE1_WFE    | \
+              PWR_CTRL1_USE_CORE0_WFE    | \
+              PWR_CTRL1_USE_CORE1_WFI    | \
+              PWR_CTRL1_USE_CORE0_WFI;
+        __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+
+        /*
+         * Enable arm clock up (on exiting idle). Set arm divider
+         * ratios when not in idle along with the standby duration
+         * ratios.
+         */
+        tmp = PWR_CTRL2_DIV2_UP_EN       | \
+              PWR_CTRL2_DIV1_UP_EN       | \
+              PWR_CTRL2_DUR_STANDBY2_VAL | \
+              PWR_CTRL2_DUR_STANDBY1_VAL | \
+              PWR_CTRL2_CORE2_UP_RATIO   | \
+              PWR_CTRL2_CORE1_UP_RATIO;
+        __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+}
+
 static int __init exynos4_init_cpuidle(void)
 {
         int i, max_cpuidle_state, cpu_id;
         struct cpuidle_device *device;
         struct cpuidle_driver *drv = &exynos4_idle_driver;
 
+        if (soc_is_exynos5250())
+                exynos5_core_down_clk();
+
         /* Setup cpuidle driver */
         drv->state_count = (sizeof(exynos4_cpuidle_set) /
                                        sizeof(struct cpuidle_state));
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 8c9b38c9c504..d36ad76ad6a4 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -267,6 +267,9 @@
 #define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
 #define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
 
+#define EXYNOS5_PWR_CTRL1                       EXYNOS_CLKREG(0x01020)
+#define EXYNOS5_PWR_CTRL2                       EXYNOS_CLKREG(0x01024)
+
 #define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
 #define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
 
@@ -344,6 +347,22 @@
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
 
+#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 84428e72cf5e..3f30aa1ae354 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -15,6 +15,7 @@
 #include <mach/map.h>
 
 #define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
+#define S5P_SYSREG(x)                           (S3C_VA_SYS + (x))
 
 #define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
 
@@ -231,6 +232,8 @@
 
 /* For EXYNOS5 */
 
+#define EXYNOS5_SYS_I2C_CFG                                     S5P_SYSREG(0x0234)
+
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
 #define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 929de766d490..f038c8cadca4 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -13,11 +13,12 @@
 #include <linux/of_fdt.h>
 #include <linux/serial_core.h>
 #include <linux/memblock.h>
-#include <linux/of_fdt.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 #include <mach/map.h>
+#include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
@@ -124,6 +125,28 @@ static void __init exynos5_dt_map_io(void)
 
 static void __init exynos5_dt_machine_init(void)
 {
+        struct device_node *i2c_np;
+        const char *i2c_compat = "samsung,s3c2440-i2c";
+        unsigned int tmp;
+
+        /*
+         * Exynos5's legacy i2c controller and new high speed i2c
+         * controller have muxed interrupt sources. By default the
+         * interrupts for 4-channel HS-I2C controller are enabled.
+         * If node for first four channels of legacy i2c controller
+         * are available then re-configure the interrupts via the
+         * system register.
+         */
+        for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+                if (of_device_is_available(i2c_np)) {
+                        if (of_alias_get_id(i2c_np, "i2c") < 4) {
+                                tmp = readl(EXYNOS5_SYS_I2C_CFG);
+                                writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
+                                                EXYNOS5_SYS_I2C_CFG);
+                        }
+                }
+        }
+
         if (of_machine_is_compatible("samsung,exynos5250"))
                 of_platform_populate(NULL, of_default_bus_match_table,
                                      exynos5250_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 8df6ec547f78..b9b539cac81e 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -62,6 +62,10 @@ static struct sleep_save exynos4_vpll_save[] = {
         SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
+static struct sleep_save exynos5_sys_save[] = {
+        SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
+};
+
 static struct sleep_save exynos_core_save[] = {
         /* SROM side */
         SAVE_ITEM(S5P_SROM_BW),
@@ -101,6 +105,7 @@ static void exynos_pm_prepare(void)
                 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
                 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
         } else {
+                s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
@@ -304,6 +309,10 @@ static void exynos_pm_resume(void)
         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 
+        if (soc_is_exynos5250())
+                s3c_pm_do_restore(exynos5_sys_save,
+                        ARRAY_SIZE(exynos5_sys_save));
+
         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
         if (!soc_is_exynos5250()) {