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authorKukjin Kim <kgene.kim@samsung.com>2012-05-19 14:01:26 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-05-19 14:01:26 -0400
commitab5a4e6381d27a6554e6833383e536773e3a6ec1 (patch)
tree88cfa18c33229cea756c2308607c26c1f19e9203 /arch/arm/mach-exynos
parent36be50515fe2aef61533b516fa2576a2c7fe7664 (diff)
parent5ddfa8428b9f21453b1160846143e0b50d51b27c (diff)
Merge branch 'next/devel-samsung' into next/devel-samsung-2
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig24
-rw-r--r--arch/arm/mach-exynos/Makefile7
-rw-r--r--arch/arm/mach-exynos/Makefile.boot3
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c79
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c11
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c38
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c90
-rw-r--r--arch/arm/mach-exynos/dev-drm.c29
-rw-r--r--arch/arm/mach-exynos/dev-sysmmu.c457
-rw-r--r--arch/arm/mach-exynos/dma.c141
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h25
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h41
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h10
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-sysmmu.h28
-rw-r--r--arch/arm/mach-exynos/include/mach/spi-clocks.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/sysmmu.h88
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c1
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c1
-rw-r--r--arch/arm/mach-exynos/pm.c2
-rw-r--r--arch/arm/mach-exynos/pmu.c24
22 files changed, 732 insertions, 376 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b8df521fb68e..5893e2397da1 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250" 61 bool "SAMSUNG EXYNOS5250"
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select SAMSUNG_DMADEV
64 help 65 help
65 Enable EXYNOS5250 SoC support 66 Enable EXYNOS5250 SoC support
66 67
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
70 help 71 help
71 Use MCT (Multi Core Timer) as kernel timers 72 Use MCT (Multi Core Timer) as kernel timers
72 73
73config EXYNOS4_DEV_DMA 74config EXYNOS_DEV_DMA
74 bool 75 bool
75 help 76 help
76 Compile in amba device definitions for DMA controller 77 Compile in amba device definitions for DMA controller
@@ -80,15 +81,20 @@ config EXYNOS4_DEV_AHCI
80 help 81 help
81 Compile in platform device definitions for AHCI 82 Compile in platform device definitions for AHCI
82 83
84config EXYNOS_DEV_DRM
85 bool
86 help
87 Compile in platform device definitions for core DRM device
88
83config EXYNOS4_SETUP_FIMD0 89config EXYNOS4_SETUP_FIMD0
84 bool 90 bool
85 help 91 help
86 Common setup code for FIMD0. 92 Common setup code for FIMD0.
87 93
88config EXYNOS4_DEV_SYSMMU 94config EXYNOS_DEV_SYSMMU
89 bool 95 bool
90 help 96 help
91 Common setup code for SYSTEM MMU in EXYNOS4 97 Common setup code for SYSTEM MMU in EXYNOS platforms
92 98
93config EXYNOS4_DEV_DWMCI 99config EXYNOS4_DEV_DWMCI
94 bool 100 bool
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
161 help 167 help
162 Common setup code for USB PHY controller 168 Common setup code for USB PHY controller
163 169
164config EXYNOS4_SETUP_SPI 170config EXYNOS_SETUP_SPI
165 bool 171 bool
166 help 172 help
167 Common setup code for SPI GPIO configurations. 173 Common setup code for SPI GPIO configurations.
@@ -200,12 +206,12 @@ config MACH_SMDKV310
200 select S3C_DEV_HSMMC2 206 select S3C_DEV_HSMMC2
201 select S3C_DEV_HSMMC3 207 select S3C_DEV_HSMMC3
202 select SAMSUNG_DEV_BACKLIGHT 208 select SAMSUNG_DEV_BACKLIGHT
209 select EXYNOS_DEV_SYSMMU
203 select EXYNOS4_DEV_AHCI 210 select EXYNOS4_DEV_AHCI
204 select SAMSUNG_DEV_KEYPAD 211 select SAMSUNG_DEV_KEYPAD
205 select EXYNOS4_DEV_DMA 212 select EXYNOS4_DEV_DMA
206 select SAMSUNG_DEV_PWM 213 select SAMSUNG_DEV_PWM
207 select EXYNOS4_DEV_USB_OHCI 214 select EXYNOS4_DEV_USB_OHCI
208 select EXYNOS4_DEV_SYSMMU
209 select EXYNOS4_SETUP_FIMD0 215 select EXYNOS4_SETUP_FIMD0
210 select EXYNOS4_SETUP_I2C1 216 select EXYNOS4_SETUP_I2C1
211 select EXYNOS4_SETUP_KEYPAD 217 select EXYNOS4_SETUP_KEYPAD
@@ -223,8 +229,7 @@ config MACH_ARMLEX4210
223 select S3C_DEV_HSMMC2 229 select S3C_DEV_HSMMC2
224 select S3C_DEV_HSMMC3 230 select S3C_DEV_HSMMC3
225 select EXYNOS4_DEV_AHCI 231 select EXYNOS4_DEV_AHCI
226 select EXYNOS4_DEV_DMA 232 select EXYNOS_DEV_DMA
227 select EXYNOS4_DEV_SYSMMU
228 select EXYNOS4_SETUP_SDHCI 233 select EXYNOS4_SETUP_SDHCI
229 help 234 help
230 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 235 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -254,6 +259,7 @@ config MACH_UNIVERSAL_C210
254 select S5P_DEV_MFC 259 select S5P_DEV_MFC
255 select S5P_DEV_ONENAND 260 select S5P_DEV_ONENAND
256 select S5P_DEV_TV 261 select S5P_DEV_TV
262 select EXYNOS_DEV_SYSMMU
257 select EXYNOS4_DEV_DMA 263 select EXYNOS4_DEV_DMA
258 select EXYNOS4_SETUP_FIMD0 264 select EXYNOS4_SETUP_FIMD0
259 select EXYNOS4_SETUP_I2C1 265 select EXYNOS4_SETUP_I2C1
@@ -325,6 +331,7 @@ config MACH_ORIGEN
325 select S5P_DEV_USB_EHCI 331 select S5P_DEV_USB_EHCI
326 select SAMSUNG_DEV_BACKLIGHT 332 select SAMSUNG_DEV_BACKLIGHT
327 select SAMSUNG_DEV_PWM 333 select SAMSUNG_DEV_PWM
334 select EXYNOS_DEV_SYSMMU
328 select EXYNOS4_DEV_DMA 335 select EXYNOS4_DEV_DMA
329 select EXYNOS4_DEV_USB_OHCI 336 select EXYNOS4_DEV_USB_OHCI
330 select EXYNOS4_SETUP_FIMD0 337 select EXYNOS4_SETUP_FIMD0
@@ -348,7 +355,8 @@ config MACH_SMDK4212
348 select SAMSUNG_DEV_BACKLIGHT 355 select SAMSUNG_DEV_BACKLIGHT
349 select SAMSUNG_DEV_KEYPAD 356 select SAMSUNG_DEV_KEYPAD
350 select SAMSUNG_DEV_PWM 357 select SAMSUNG_DEV_PWM
351 select EXYNOS4_DEV_DMA 358 select EXYNOS_DEV_SYSMMU
359 select EXYNOS_DEV_DMA
352 select EXYNOS4_SETUP_I2C1 360 select EXYNOS4_SETUP_I2C1
353 select EXYNOS4_SETUP_I2C3 361 select EXYNOS4_SETUP_I2C3
354 select EXYNOS4_SETUP_I2C7 362 select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8631840d1b5e..440a637c76f1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
50obj-y += dev-uart.o 50obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
54obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 53obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 54obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 55obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
56obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
57obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
57 58
58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 59obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
68obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 69obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
69obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 70obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
70obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 71obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
71obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o 72obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index b9862e22bf10..31bd181b0514 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,2 +1,5 @@
1 zreladdr-y += 0x40008000 1 zreladdr-y += 0x40008000
2params_phys-y := 0x40000100 2params_phys-y := 0x40000100
3
4dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
5dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 6efd1e5919fd..bcb7db453145 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -168,7 +168,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); 168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169} 169}
170 170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) 171int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{ 172{
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); 173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174} 174}
@@ -198,6 +198,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); 198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199} 199}
200 200
201int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202{
203 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
204}
205
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 206static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202{ 207{
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 208 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@@ -678,61 +683,55 @@ static struct clk exynos4_init_clocks_off[] = {
678 .enable = exynos4_clk_ip_peril_ctrl, 683 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 14), 684 .ctrlbit = (1 << 14),
680 }, { 685 }, {
681 .name = "SYSMMU_MDMA", 686 .name = SYSMMU_CLOCK_NAME,
687 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
688 .enable = exynos4_clk_ip_mfc_ctrl,
689 .ctrlbit = (1 << 1),
690 }, {
691 .name = SYSMMU_CLOCK_NAME,
692 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
693 .enable = exynos4_clk_ip_mfc_ctrl,
694 .ctrlbit = (1 << 2),
695 }, {
696 .name = SYSMMU_CLOCK_NAME,
697 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
698 .enable = exynos4_clk_ip_tv_ctrl,
699 .ctrlbit = (1 << 4),
700 }, {
701 .name = SYSMMU_CLOCK_NAME,
702 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
703 .enable = exynos4_clk_ip_cam_ctrl,
704 .ctrlbit = (1 << 11),
705 }, {
706 .name = SYSMMU_CLOCK_NAME,
707 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
682 .enable = exynos4_clk_ip_image_ctrl, 708 .enable = exynos4_clk_ip_image_ctrl,
683 .ctrlbit = (1 << 5), 709 .ctrlbit = (1 << 4),
684 }, { 710 }, {
685 .name = "SYSMMU_FIMC0", 711 .name = SYSMMU_CLOCK_NAME,
712 .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
686 .enable = exynos4_clk_ip_cam_ctrl, 713 .enable = exynos4_clk_ip_cam_ctrl,
687 .ctrlbit = (1 << 7), 714 .ctrlbit = (1 << 7),
688 }, { 715 }, {
689 .name = "SYSMMU_FIMC1", 716 .name = SYSMMU_CLOCK_NAME,
717 .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
690 .enable = exynos4_clk_ip_cam_ctrl, 718 .enable = exynos4_clk_ip_cam_ctrl,
691 .ctrlbit = (1 << 8), 719 .ctrlbit = (1 << 8),
692 }, { 720 }, {
693 .name = "SYSMMU_FIMC2", 721 .name = SYSMMU_CLOCK_NAME,
722 .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
694 .enable = exynos4_clk_ip_cam_ctrl, 723 .enable = exynos4_clk_ip_cam_ctrl,
695 .ctrlbit = (1 << 9), 724 .ctrlbit = (1 << 9),
696 }, { 725 }, {
697 .name = "SYSMMU_FIMC3", 726 .name = SYSMMU_CLOCK_NAME,
727 .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
698 .enable = exynos4_clk_ip_cam_ctrl, 728 .enable = exynos4_clk_ip_cam_ctrl,
699 .ctrlbit = (1 << 10), 729 .ctrlbit = (1 << 10),
700 }, { 730 }, {
701 .name = "SYSMMU_JPEG", 731 .name = SYSMMU_CLOCK_NAME,
702 .enable = exynos4_clk_ip_cam_ctrl, 732 .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
703 .ctrlbit = (1 << 11),
704 }, {
705 .name = "SYSMMU_FIMD0",
706 .enable = exynos4_clk_ip_lcd0_ctrl, 733 .enable = exynos4_clk_ip_lcd0_ctrl,
707 .ctrlbit = (1 << 4), 734 .ctrlbit = (1 << 4),
708 }, {
709 .name = "SYSMMU_FIMD1",
710 .enable = exynos4_clk_ip_lcd1_ctrl,
711 .ctrlbit = (1 << 4),
712 }, {
713 .name = "SYSMMU_PCIe",
714 .enable = exynos4_clk_ip_fsys_ctrl,
715 .ctrlbit = (1 << 18),
716 }, {
717 .name = "SYSMMU_G2D",
718 .enable = exynos4_clk_ip_image_ctrl,
719 .ctrlbit = (1 << 3),
720 }, {
721 .name = "SYSMMU_ROTATOR",
722 .enable = exynos4_clk_ip_image_ctrl,
723 .ctrlbit = (1 << 4),
724 }, {
725 .name = "SYSMMU_TV",
726 .enable = exynos4_clk_ip_tv_ctrl,
727 .ctrlbit = (1 << 4),
728 }, {
729 .name = "SYSMMU_MFC_L",
730 .enable = exynos4_clk_ip_mfc_ctrl,
731 .ctrlbit = (1 << 1),
732 }, {
733 .name = "SYSMMU_MFC_R",
734 .enable = exynos4_clk_ip_mfc_ctrl,
735 .ctrlbit = (1 << 2),
736 } 735 }
737}; 736};
738 737
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index cb71c29c14d1..28a119701182 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -26,5 +26,7 @@ extern struct clk *exynos4_clkset_group_list[];
26extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); 26extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
27extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); 27extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
28extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); 28extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
29extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
30extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
29 31
30#endif /* __ASM_ARCH_CLOCK_H */ 32#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 3b131e4b6ef5..b8689ff60baf 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -26,6 +26,7 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
29#include <mach/sysmmu.h>
29 30
30#include "common.h" 31#include "common.h"
31#include "clock-exynos4.h" 32#include "clock-exynos4.h"
@@ -94,6 +95,16 @@ static struct clk init_clocks_off[] = {
94 .devname = "exynos4-fb.1", 95 .devname = "exynos4-fb.1",
95 .enable = exynos4_clk_ip_lcd1_ctrl, 96 .enable = exynos4_clk_ip_lcd1_ctrl,
96 .ctrlbit = (1 << 0), 97 .ctrlbit = (1 << 0),
98 }, {
99 .name = SYSMMU_CLOCK_NAME,
100 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
101 .enable = exynos4_clk_ip_image_ctrl,
102 .ctrlbit = (1 << 3),
103 }, {
104 .name = SYSMMU_CLOCK_NAME,
105 .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
106 .enable = exynos4_clk_ip_lcd1_ctrl,
107 .ctrlbit = (1 << 4),
97 }, 108 },
98}; 109};
99 110
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 3ecc01e06f74..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -26,6 +26,7 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
29#include <mach/sysmmu.h>
29 30
30#include "common.h" 31#include "common.h"
31#include "clock-exynos4.h" 32#include "clock-exynos4.h"
@@ -39,6 +40,16 @@ static struct sleep_save exynos4212_clock_save[] = {
39}; 40};
40#endif 41#endif
41 42
43static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
44{
45 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
46}
47
48static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
49{
50 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
51}
52
42static struct clk *clk_src_mpll_user_list[] = { 53static struct clk *clk_src_mpll_user_list[] = {
43 [0] = &clk_fin_mpll, 54 [0] = &clk_fin_mpll,
44 [1] = &exynos4_clk_mout_mpll.clk, 55 [1] = &exynos4_clk_mout_mpll.clk,
@@ -66,7 +77,32 @@ static struct clksrc_clk clksrcs[] = {
66}; 77};
67 78
68static struct clk init_clocks_off[] = { 79static struct clk init_clocks_off[] = {
69 /* nothing here yet */ 80 {
81 .name = SYSMMU_CLOCK_NAME,
82 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
83 .enable = exynos4_clk_ip_dmc_ctrl,
84 .ctrlbit = (1 << 24),
85 }, {
86 .name = SYSMMU_CLOCK_NAME,
87 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
88 .enable = exynos4212_clk_ip_isp0_ctrl,
89 .ctrlbit = (7 << 8),
90 }, {
91 .name = SYSMMU_CLOCK_NAME2,
92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
93 .enable = exynos4212_clk_ip_isp1_ctrl,
94 .ctrlbit = (1 << 4),
95 }, {
96 .name = "flite",
97 .devname = "exynos-fimc-lite.0",
98 .enable = exynos4212_clk_ip_isp0_ctrl,
99 .ctrlbit = (1 << 4),
100 }, {
101 .name = "flite",
102 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl,
104 .ctrlbit = (1 << 3),
105 }
70}; 106};
71 107
72#ifdef CONFIG_PM_SLEEP 108#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 7ac6ff4c46bd..9f87a07b0bf8 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); 82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
83} 83}
84 84
85static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
86{
87 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
88}
89
85static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable) 90static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
86{ 91{
87 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable); 92 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
127 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable); 132 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
128} 133}
129 134
135static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
138}
139
140static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
143}
144
145static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
148}
149
130/* Core list of CMU_CPU side */ 150/* Core list of CMU_CPU side */
131 151
132static struct clksrc_clk exynos5_clk_mout_apll = { 152static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
630 .parent = &exynos5_clk_aclk_66.clk, 650 .parent = &exynos5_clk_aclk_66.clk,
631 .enable = exynos5_clk_ip_peric_ctrl, 651 .enable = exynos5_clk_ip_peric_ctrl,
632 .ctrlbit = (1 << 14), 652 .ctrlbit = (1 << 14),
653 }, {
654 .name = SYSMMU_CLOCK_NAME,
655 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
656 .enable = &exynos5_clk_ip_mfc_ctrl,
657 .ctrlbit = (1 << 1),
658 }, {
659 .name = SYSMMU_CLOCK_NAME,
660 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
661 .enable = &exynos5_clk_ip_mfc_ctrl,
662 .ctrlbit = (1 << 2),
663 }, {
664 .name = SYSMMU_CLOCK_NAME,
665 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
666 .enable = &exynos5_clk_ip_disp1_ctrl,
667 .ctrlbit = (1 << 9)
668 }, {
669 .name = SYSMMU_CLOCK_NAME,
670 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
671 .enable = &exynos5_clk_ip_gen_ctrl,
672 .ctrlbit = (1 << 7),
673 }, {
674 .name = SYSMMU_CLOCK_NAME,
675 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
676 .enable = &exynos5_clk_ip_gen_ctrl,
677 .ctrlbit = (1 << 6)
678 }, {
679 .name = SYSMMU_CLOCK_NAME,
680 .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
681 .enable = &exynos5_clk_ip_gscl_ctrl,
682 .ctrlbit = (1 << 7),
683 }, {
684 .name = SYSMMU_CLOCK_NAME,
685 .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
686 .enable = &exynos5_clk_ip_gscl_ctrl,
687 .ctrlbit = (1 << 8),
688 }, {
689 .name = SYSMMU_CLOCK_NAME,
690 .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
691 .enable = &exynos5_clk_ip_gscl_ctrl,
692 .ctrlbit = (1 << 9),
693 }, {
694 .name = SYSMMU_CLOCK_NAME,
695 .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
696 .enable = &exynos5_clk_ip_gscl_ctrl,
697 .ctrlbit = (1 << 10),
698 }, {
699 .name = SYSMMU_CLOCK_NAME,
700 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
701 .enable = &exynos5_clk_ip_isp0_ctrl,
702 .ctrlbit = (0x3F << 8),
703 }, {
704 .name = SYSMMU_CLOCK_NAME2,
705 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
706 .enable = &exynos5_clk_ip_isp1_ctrl,
707 .ctrlbit = (0xF << 4),
708 }, {
709 .name = SYSMMU_CLOCK_NAME,
710 .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
711 .enable = &exynos5_clk_ip_gscl_ctrl,
712 .ctrlbit = (1 << 11),
713 }, {
714 .name = SYSMMU_CLOCK_NAME,
715 .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
716 .enable = &exynos5_clk_ip_gscl_ctrl,
717 .ctrlbit = (1 << 12),
718 }, {
719 .name = SYSMMU_CLOCK_NAME,
720 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
721 .enable = &exynos5_clk_ip_acp_ctrl,
722 .ctrlbit = (1 << 7)
633 } 723 }
634}; 724};
635 725
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 000000000000..17c9c6ecc2e0
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm/mach-exynos/dev-drm.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS - core DRM device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20
21static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
22
23struct platform_device exynos_device_drm = {
24 .name = "exynos-drm",
25 .dev = {
26 .dma_mask = &exynos_drm_dma_mask,
27 .coherent_dma_mask = DMA_BIT_MASK(32),
28 }
29};
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
index 781563fcb156..c5b1ea301df0 100644
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ b/arch/arm/mach-exynos/dev-sysmmu.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-exynos4/dev-sysmmu.c 1/* linux/arch/arm/mach-exynos/dev-sysmmu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * EXYNOS4 - System MMU support 6 * EXYNOS - System MMU support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -12,222 +12,263 @@
12 12
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/export.h> 15
16#include <plat/cpu.h>
16 17
17#include <mach/map.h> 18#include <mach/map.h>
18#include <mach/irqs.h> 19#include <mach/irqs.h>
19#include <mach/sysmmu.h> 20#include <mach/sysmmu.h>
20#include <plat/s5p-clock.h>
21
22/* These names must be equal to the clock names in mach-exynos4/clock.c */
23const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
24 "SYSMMU_MDMA" ,
25 "SYSMMU_SSS" ,
26 "SYSMMU_FIMC0" ,
27 "SYSMMU_FIMC1" ,
28 "SYSMMU_FIMC2" ,
29 "SYSMMU_FIMC3" ,
30 "SYSMMU_JPEG" ,
31 "SYSMMU_FIMD0" ,
32 "SYSMMU_FIMD1" ,
33 "SYSMMU_PCIe" ,
34 "SYSMMU_G2D" ,
35 "SYSMMU_ROTATOR",
36 "SYSMMU_MDMA2" ,
37 "SYSMMU_TV" ,
38 "SYSMMU_MFC_L" ,
39 "SYSMMU_MFC_R" ,
40};
41 21
42static struct resource exynos4_sysmmu_resource[] = { 22static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
43 [0] = { 23
44 .start = EXYNOS4_PA_SYSMMU_MDMA, 24#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
45 .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1, 25static struct sysmmu_platform_data platdata_##ipname = { \
46 .flags = IORESOURCE_MEM, 26 .dbgname = #ipname, \
47 }, 27}; \
48 [1] = { 28struct platform_device SYSMMU_PLATDEV(ipname) = \
49 .start = IRQ_SYSMMU_MDMA0_0, 29{ \
50 .end = IRQ_SYSMMU_MDMA0_0, 30 .name = SYSMMU_DEVNAME_BASE, \
51 .flags = IORESOURCE_IRQ, 31 .id = devid, \
52 }, 32 .dev = { \
53 [2] = { 33 .dma_mask = &exynos_sysmmu_dma_mask, \
54 .start = EXYNOS4_PA_SYSMMU_SSS, 34 .coherent_dma_mask = DMA_BIT_MASK(32), \
55 .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1, 35 .platform_data = &platdata_##ipname, \
56 .flags = IORESOURCE_MEM, 36 }, \
57 }, 37}
58 [3] = { 38
59 .start = IRQ_SYSMMU_SSS_0, 39SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
60 .end = IRQ_SYSMMU_SSS_0, 40SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
61 .flags = IORESOURCE_IRQ, 41SYSMMU_PLATFORM_DEVICE(tv, 2);
62 }, 42SYSMMU_PLATFORM_DEVICE(jpeg, 3);
63 [4] = { 43SYSMMU_PLATFORM_DEVICE(rot, 4);
64 .start = EXYNOS4_PA_SYSMMU_FIMC0, 44SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
65 .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1, 45SYSMMU_PLATFORM_DEVICE(fimc1, 6);
66 .flags = IORESOURCE_MEM, 46SYSMMU_PLATFORM_DEVICE(fimc2, 7);
67 }, 47SYSMMU_PLATFORM_DEVICE(fimc3, 8);
68 [5] = { 48SYSMMU_PLATFORM_DEVICE(gsc0, 5);
69 .start = IRQ_SYSMMU_FIMC0_0, 49SYSMMU_PLATFORM_DEVICE(gsc1, 6);
70 .end = IRQ_SYSMMU_FIMC0_0, 50SYSMMU_PLATFORM_DEVICE(gsc2, 7);
71 .flags = IORESOURCE_IRQ, 51SYSMMU_PLATFORM_DEVICE(gsc3, 8);
72 }, 52SYSMMU_PLATFORM_DEVICE(isp, 9);
73 [6] = { 53SYSMMU_PLATFORM_DEVICE(fimd0, 10);
74 .start = EXYNOS4_PA_SYSMMU_FIMC1, 54SYSMMU_PLATFORM_DEVICE(fimd1, 11);
75 .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1, 55SYSMMU_PLATFORM_DEVICE(camif0, 12);
76 .flags = IORESOURCE_MEM, 56SYSMMU_PLATFORM_DEVICE(camif1, 13);
77 }, 57SYSMMU_PLATFORM_DEVICE(2d, 14);
78 [7] = { 58
79 .start = IRQ_SYSMMU_FIMC1_0, 59#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
80 .end = IRQ_SYSMMU_FIMC1_0, 60
81 .flags = IORESOURCE_IRQ, 61#define SYSMMU_RESOURCE(core, ipname) \
82 }, 62 static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
83 [8] = { 63
84 .start = EXYNOS4_PA_SYSMMU_FIMC2, 64#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
85 .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1, 65 DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
86 .flags = IORESOURCE_MEM, 66 DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
87 }, 67
88 [9] = { 68#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
89 .start = IRQ_SYSMMU_FIMC2_0, 69 SYSMMU_RESOURCE(core, ipname) { \
90 .end = IRQ_SYSMMU_FIMC2_0, 70 DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
91 .flags = IORESOURCE_IRQ, 71 }
92 },
93 [10] = {
94 .start = EXYNOS4_PA_SYSMMU_FIMC3,
95 .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [11] = {
99 .start = IRQ_SYSMMU_FIMC3_0,
100 .end = IRQ_SYSMMU_FIMC3_0,
101 .flags = IORESOURCE_IRQ,
102 },
103 [12] = {
104 .start = EXYNOS4_PA_SYSMMU_JPEG,
105 .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [13] = {
109 .start = IRQ_SYSMMU_JPEG_0,
110 .end = IRQ_SYSMMU_JPEG_0,
111 .flags = IORESOURCE_IRQ,
112 },
113 [14] = {
114 .start = EXYNOS4_PA_SYSMMU_FIMD0,
115 .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
116 .flags = IORESOURCE_MEM,
117 },
118 [15] = {
119 .start = IRQ_SYSMMU_LCD0_M0_0,
120 .end = IRQ_SYSMMU_LCD0_M0_0,
121 .flags = IORESOURCE_IRQ,
122 },
123 [16] = {
124 .start = EXYNOS4_PA_SYSMMU_FIMD1,
125 .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
126 .flags = IORESOURCE_MEM,
127 },
128 [17] = {
129 .start = IRQ_SYSMMU_LCD1_M1_0,
130 .end = IRQ_SYSMMU_LCD1_M1_0,
131 .flags = IORESOURCE_IRQ,
132 },
133 [18] = {
134 .start = EXYNOS4_PA_SYSMMU_PCIe,
135 .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [19] = {
139 .start = IRQ_SYSMMU_PCIE_0,
140 .end = IRQ_SYSMMU_PCIE_0,
141 .flags = IORESOURCE_IRQ,
142 },
143 [20] = {
144 .start = EXYNOS4_PA_SYSMMU_G2D,
145 .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [21] = {
149 .start = IRQ_SYSMMU_2D_0,
150 .end = IRQ_SYSMMU_2D_0,
151 .flags = IORESOURCE_IRQ,
152 },
153 [22] = {
154 .start = EXYNOS4_PA_SYSMMU_ROTATOR,
155 .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 [23] = {
159 .start = IRQ_SYSMMU_ROTATOR_0,
160 .end = IRQ_SYSMMU_ROTATOR_0,
161 .flags = IORESOURCE_IRQ,
162 },
163 [24] = {
164 .start = EXYNOS4_PA_SYSMMU_MDMA2,
165 .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 [25] = {
169 .start = IRQ_SYSMMU_MDMA1_0,
170 .end = IRQ_SYSMMU_MDMA1_0,
171 .flags = IORESOURCE_IRQ,
172 },
173 [26] = {
174 .start = EXYNOS4_PA_SYSMMU_TV,
175 .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
176 .flags = IORESOURCE_MEM,
177 },
178 [27] = {
179 .start = IRQ_SYSMMU_TV_M0_0,
180 .end = IRQ_SYSMMU_TV_M0_0,
181 .flags = IORESOURCE_IRQ,
182 },
183 [28] = {
184 .start = EXYNOS4_PA_SYSMMU_MFC_L,
185 .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 [29] = {
189 .start = IRQ_SYSMMU_MFC_M0_0,
190 .end = IRQ_SYSMMU_MFC_M0_0,
191 .flags = IORESOURCE_IRQ,
192 },
193 [30] = {
194 .start = EXYNOS4_PA_SYSMMU_MFC_R,
195 .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
196 .flags = IORESOURCE_MEM,
197 },
198 [31] = {
199 .start = IRQ_SYSMMU_MFC_M1_0,
200 .end = IRQ_SYSMMU_MFC_M1_0,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204 72
205struct platform_device exynos4_device_sysmmu = { 73struct sysmmu_resource_map {
206 .name = "s5p-sysmmu", 74 struct platform_device *pdev;
207 .id = 32, 75 struct resource *res;
208 .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource), 76 u32 rnum;
209 .resource = exynos4_sysmmu_resource, 77 struct device *pdd;
78 char *clocknames;
210}; 79};
211EXPORT_SYMBOL(exynos4_device_sysmmu);
212 80
213static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM]; 81#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
214void sysmmu_clk_init(struct device *dev, sysmmu_ips ips) 82 .pdev = &SYSMMU_PLATDEV(ipname), \
215{ 83 .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
216 sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]); 84 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
217 if (IS_ERR(sysmmu_clk[ips])) 85 .clocknames = SYSMMU_CLOCK_NAME, \
218 sysmmu_clk[ips] = NULL;
219 else
220 clk_put(sysmmu_clk[ips]);
221} 86}
222 87
223void sysmmu_clk_enable(sysmmu_ips ips) 88#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
224{ 89 .pdev = &SYSMMU_PLATDEV(ipname), \
225 if (sysmmu_clk[ips]) 90 .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
226 clk_enable(sysmmu_clk[ips]); 91 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
92 .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
93}
94
95#ifdef CONFIG_EXYNOS_DEV_PD
96#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
97 .pdev = &SYSMMU_PLATDEV(ipname), \
98 .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
99 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
100 .clocknames = SYSMMU_CLOCK_NAME, \
101 .pdd = &exynos##core##_device_pd[pd].dev, \
102}
103
104#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
105 .pdev = &SYSMMU_PLATDEV(ipname), \
106 .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
107 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
108 .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
109 .pdd = &exynos##core##_device_pd[pd].dev, \
227} 110}
111#else
112#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
113 SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
114#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
115 SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
116
117#endif /* CONFIG_EXYNOS_DEV_PD */
118
119#ifdef CONFIG_ARCH_EXYNOS4
120SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
121SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
122SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
123SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
124SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
125SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
126SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
127SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
128SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
129SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
130SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
131SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
132SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
133SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
134SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
135SYSMMU_RESOURCE(EXYNOS4, isp) {
136 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
137 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
138 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
139 DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
140};
141
142static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
143 SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
144 SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
145 SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
146 SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
147 SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
148 SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
149 SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
150 SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
151 SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
152 SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
153};
154
155static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
156 SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
157 SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
158};
159
160static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
161 SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
162 SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
163 SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
164 SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
165};
166#endif /* CONFIG_ARCH_EXYNOS4 */
228 167
229void sysmmu_clk_disable(sysmmu_ips ips) 168#ifdef CONFIG_ARCH_EXYNOS5
169SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
170SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
171SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
172SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
173SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
174SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
175SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
176SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
177SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
178SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
179SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
180SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
181SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
182SYSMMU_RESOURCE(EXYNOS5, isp) {
183 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
184 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
185 DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
186 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
187 DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
188 DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
189 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
190 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
191 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
192 DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
193};
194
195static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
196 SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
197 SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
198 SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
199 SYSMMU_RESOURCE_MAPPING(5, rot, rot),
200 SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
201 SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
202 SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
203 SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
204 SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
205 SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
206 SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
207 SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
208 SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
209 SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
210};
211#endif /* CONFIG_ARCH_EXYNOS5 */
212
213static int __init init_sysmmu_platform_device(void)
230{ 214{
231 if (sysmmu_clk[ips]) 215 int i, j;
232 clk_disable(sysmmu_clk[ips]); 216 struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
217 int nmap[2] = {0, 0};
218
219#ifdef CONFIG_ARCH_EXYNOS5
220 if (soc_is_exynos5250()) {
221 resmap[0] = sysmmu_resmap5;
222 nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
223 nmap[1] = 0;
224 }
225#endif
226
227#ifdef CONFIG_ARCH_EXYNOS4
228 if (resmap[0] == NULL) {
229 resmap[0] = sysmmu_resmap4;
230 nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
231 }
232
233 if (soc_is_exynos4210()) {
234 resmap[1] = sysmmu_resmap4210;
235 nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
236 }
237
238 if (soc_is_exynos4412() || soc_is_exynos4212()) {
239 resmap[1] = sysmmu_resmap4212;
240 nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
241 }
242#endif
243
244 for (j = 0; j < 2; j++) {
245 for (i = 0; i < nmap[j]; i++) {
246 struct sysmmu_resource_map *map;
247 struct sysmmu_platform_data *platdata;
248
249 map = &resmap[j][i];
250
251 map->pdev->dev.parent = map->pdd;
252
253 platdata = map->pdev->dev.platform_data;
254 platdata->clockname = map->clocknames;
255
256 if (platform_device_add_resources(map->pdev, map->res,
257 map->rnum)) {
258 pr_err("%s: Failed to add device resources for "
259 "%s.%d\n", __func__,
260 map->pdev->name, map->pdev->id);
261 continue;
262 }
263
264 if (platform_device_register(map->pdev)) {
265 pr_err("%s: Failed to register %s.%d\n",
266 __func__, map->pdev->name,
267 map->pdev->id);
268 }
269 }
270 }
271
272 return 0;
233} 273}
274arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa4503205..f60b66dbcf84 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
103 DMACH_MIPI_HSI5, 103 DMACH_MIPI_HSI5,
104}; 104};
105 105
106struct dma_pl330_platdata exynos4_pdma0_pdata; 106static u8 exynos5250_pdma0_peri[] = {
107 DMACH_PCM0_RX,
108 DMACH_PCM0_TX,
109 DMACH_PCM2_RX,
110 DMACH_PCM2_TX,
111 DMACH_SPI0_RX,
112 DMACH_SPI0_TX,
113 DMACH_SPI2_RX,
114 DMACH_SPI2_TX,
115 DMACH_I2S0S_TX,
116 DMACH_I2S0_RX,
117 DMACH_I2S0_TX,
118 DMACH_I2S2_RX,
119 DMACH_I2S2_TX,
120 DMACH_UART0_RX,
121 DMACH_UART0_TX,
122 DMACH_UART2_RX,
123 DMACH_UART2_TX,
124 DMACH_UART4_RX,
125 DMACH_UART4_TX,
126 DMACH_SLIMBUS0_RX,
127 DMACH_SLIMBUS0_TX,
128 DMACH_SLIMBUS2_RX,
129 DMACH_SLIMBUS2_TX,
130 DMACH_SLIMBUS4_RX,
131 DMACH_SLIMBUS4_TX,
132 DMACH_AC97_MICIN,
133 DMACH_AC97_PCMIN,
134 DMACH_AC97_PCMOUT,
135 DMACH_MIPI_HSI0,
136 DMACH_MIPI_HSI2,
137 DMACH_MIPI_HSI4,
138 DMACH_MIPI_HSI6,
139};
140
141static struct dma_pl330_platdata exynos_pdma0_pdata;
107 142
108static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, 143static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
109 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata); 144 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
110 145
111static u8 exynos4210_pdma1_peri[] = { 146static u8 exynos4210_pdma1_peri[] = {
112 DMACH_PCM0_RX, 147 DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
169 DMACH_MIPI_HSI7, 204 DMACH_MIPI_HSI7,
170}; 205};
171 206
172static struct dma_pl330_platdata exynos4_pdma1_pdata; 207static u8 exynos5250_pdma1_peri[] = {
208 DMACH_PCM0_RX,
209 DMACH_PCM0_TX,
210 DMACH_PCM1_RX,
211 DMACH_PCM1_TX,
212 DMACH_SPI1_RX,
213 DMACH_SPI1_TX,
214 DMACH_PWM,
215 DMACH_SPDIF,
216 DMACH_I2S0S_TX,
217 DMACH_I2S0_RX,
218 DMACH_I2S0_TX,
219 DMACH_I2S1_RX,
220 DMACH_I2S1_TX,
221 DMACH_UART0_RX,
222 DMACH_UART0_TX,
223 DMACH_UART1_RX,
224 DMACH_UART1_TX,
225 DMACH_UART3_RX,
226 DMACH_UART3_TX,
227 DMACH_SLIMBUS1_RX,
228 DMACH_SLIMBUS1_TX,
229 DMACH_SLIMBUS3_RX,
230 DMACH_SLIMBUS3_TX,
231 DMACH_SLIMBUS5_RX,
232 DMACH_SLIMBUS5_TX,
233 DMACH_SLIMBUS0AUX_RX,
234 DMACH_SLIMBUS0AUX_TX,
235 DMACH_DISP1,
236 DMACH_MIPI_HSI1,
237 DMACH_MIPI_HSI3,
238 DMACH_MIPI_HSI5,
239 DMACH_MIPI_HSI7,
240};
173 241
174static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, 242static struct dma_pl330_platdata exynos_pdma1_pdata;
175 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata); 243
244static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
245 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
176 246
177static u8 mdma_peri[] = { 247static u8 mdma_peri[] = {
178 DMACH_MTOM_0, 248 DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
185 DMACH_MTOM_7, 255 DMACH_MTOM_7,
186}; 256};
187 257
188static struct dma_pl330_platdata exynos4_mdma1_pdata = { 258static struct dma_pl330_platdata exynos_mdma1_pdata = {
189 .nr_valid_peri = ARRAY_SIZE(mdma_peri), 259 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
190 .peri_id = mdma_peri, 260 .peri_id = mdma_peri,
191}; 261};
192 262
193static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, 263static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
194 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata); 264 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
195 265
196static int __init exynos4_dma_init(void) 266static int __init exynos_dma_init(void)
197{ 267{
198 if (of_have_populated_dt()) 268 if (of_have_populated_dt())
199 return 0; 269 return 0;
200 270
201 if (soc_is_exynos4210()) { 271 if (soc_is_exynos4210()) {
202 exynos4_pdma0_pdata.nr_valid_peri = 272 exynos_pdma0_pdata.nr_valid_peri =
203 ARRAY_SIZE(exynos4210_pdma0_peri); 273 ARRAY_SIZE(exynos4210_pdma0_peri);
204 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri; 274 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
205 exynos4_pdma1_pdata.nr_valid_peri = 275 exynos_pdma1_pdata.nr_valid_peri =
206 ARRAY_SIZE(exynos4210_pdma1_peri); 276 ARRAY_SIZE(exynos4210_pdma1_peri);
207 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri; 277 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
208 } else if (soc_is_exynos4212() || soc_is_exynos4412()) { 278 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
209 exynos4_pdma0_pdata.nr_valid_peri = 279 exynos_pdma0_pdata.nr_valid_peri =
210 ARRAY_SIZE(exynos4212_pdma0_peri); 280 ARRAY_SIZE(exynos4212_pdma0_peri);
211 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri; 281 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
212 exynos4_pdma1_pdata.nr_valid_peri = 282 exynos_pdma1_pdata.nr_valid_peri =
213 ARRAY_SIZE(exynos4212_pdma1_peri); 283 ARRAY_SIZE(exynos4212_pdma1_peri);
214 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri; 284 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
285 } else if (soc_is_exynos5250()) {
286 exynos_pdma0_pdata.nr_valid_peri =
287 ARRAY_SIZE(exynos5250_pdma0_peri);
288 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
289 exynos_pdma1_pdata.nr_valid_peri =
290 ARRAY_SIZE(exynos5250_pdma1_peri);
291 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
292
293 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
294 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
295 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
296 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
297 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
298 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
299 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
300 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
301 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
215 } 302 }
216 303
217 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 304 dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
218 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 305 dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
219 amba_device_register(&exynos4_pdma0_device, &iomem_resource); 306 amba_device_register(&exynos_pdma0_device, &iomem_resource);
220 307
221 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); 308 dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
222 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 309 dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
223 amba_device_register(&exynos4_pdma1_device, &iomem_resource); 310 amba_device_register(&exynos_pdma1_device, &iomem_resource);
224 311
225 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask); 312 dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
226 amba_device_register(&exynos4_mdma1_device, &iomem_resource); 313 amba_device_register(&exynos_mdma1_device, &iomem_resource);
227 314
228 return 0; 315 return 0;
229} 316}
230arch_initcall(exynos4_dma_init); 317arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 591e78521a9f..116167524051 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -154,6 +154,13 @@
154#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 154#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
155#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 155#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
156 156
157#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
158#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
159#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
160#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
161#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
162#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
163
157#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) 164#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
158#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) 165#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
159#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) 166#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
@@ -220,24 +227,6 @@
220#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD 227#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
221#define IRQ_PMU EXYNOS4_IRQ_PMU 228#define IRQ_PMU EXYNOS4_IRQ_PMU
222 229
223#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
224#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
225#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
226#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
227#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
228#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
229#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
230#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
231
232#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
233#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
234#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
235#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
236#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
237#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
238#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
239#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
240
241#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO 230#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
242#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC 231#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
243#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM 232#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 6e6d11ff352a..d30643ba2739 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
34 34
35#define EXYNOS4_PA_JPEG 0x11840000 35#define EXYNOS4_PA_JPEG 0x11840000
36 36
37/* x = 0...1 */
38#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
39
37#define EXYNOS4_PA_G2D 0x12800000 40#define EXYNOS4_PA_G2D 0x12800000
38 41
39#define EXYNOS4_PA_I2S0 0x03830000 42#define EXYNOS4_PA_I2S0 0x03830000
@@ -95,6 +98,7 @@
95#define EXYNOS5_PA_PDMA1 0x121B0000 98#define EXYNOS5_PA_PDMA1 0x121B0000
96 99
97#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 100#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
101#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
98#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 102#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
99#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 103#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
100#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 104#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
@@ -103,6 +107,12 @@
103#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 107#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
104#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 108#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
105#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 109#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
110#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
111#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
112#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
113#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
114#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
115#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
106#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 116#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
107#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 117#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
108#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 118#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
@@ -110,6 +120,37 @@
110#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 120#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
111#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 121#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
112#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 122#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
123
124#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
125#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
126#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
127#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
128#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
129#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
130#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
131#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
132#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
133#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
134#define EXYNOS5_PA_SYSMMU_GPS 0x12630000
135#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
136#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
137#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
138#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
139#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
140#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
141#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
142#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
143#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
144#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
145#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
146#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
147#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
148#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
149#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
150#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
151#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
152#define EXYNOS5_PA_SYSMMU_TV 0x14650000
153
113#define EXYNOS4_PA_SPI0 0x13920000 154#define EXYNOS4_PA_SPI0 0x13920000
114#define EXYNOS4_PA_SPI1 0x13930000 155#define EXYNOS4_PA_SPI1 0x13930000
115#define EXYNOS4_PA_SPI2 0x13940000 156#define EXYNOS4_PA_SPI2 0x13940000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d9578a58ae7f..dba83e91f0fd 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -135,6 +135,9 @@
135#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) 135#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
136#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) 136#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
137 137
138#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
139#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
140
138#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ 141#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
139 142
140#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) 143#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
@@ -303,6 +306,8 @@
303#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) 306#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
304 307
305#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) 308#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
309#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
310#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
306#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) 311#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
307#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) 312#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
308#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) 313#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38b5a9e..606b19907f99 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -177,7 +177,7 @@
177 177
178#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) 178#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
179 179
180/* Only for EXYNOS4212 */ 180/* Only for EXYNOS4x12 */
181#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 181#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
182#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 182#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
183#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 183#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
@@ -218,4 +218,12 @@
218#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 218#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
219#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 219#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
220 220
221/* Only for EXYNOS4412 */
222#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
223#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
224#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
225#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
226#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
227#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
228
221#endif /* __ASM_ARCH_REGS_PMU_H */ 229#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
deleted file mode 100644
index 68ff6ad08a2b..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - System MMU register
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SYSMMU_H
14#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
15
16#define S5P_MMU_CTRL 0x000
17#define S5P_MMU_CFG 0x004
18#define S5P_MMU_STATUS 0x008
19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018
22#define S5P_INT_CLEAR 0x01C
23#define S5P_PAGE_FAULT_ADDR 0x024
24#define S5P_AW_FAULT_ADDR 0x028
25#define S5P_AR_FAULT_ADDR 0x02C
26#define S5P_DEFAULT_SLAVE_ADDR 0x030
27
28#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
index 576efdf6d091..c71a5fba6a84 100644
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -11,6 +11,6 @@
11#define __ASM_ARCH_SPI_CLKS_H __FILE__ 11#define __ASM_ARCH_SPI_CLKS_H __FILE__
12 12
13/* Must source from SCLK_SPI */ 13/* Must source from SCLK_SPI */
14#define EXYNOS4_SPI_SRCCLK_SCLK 0 14#define EXYNOS_SPI_SRCCLK_SCLK 0
15 15
16#endif /* __ASM_ARCH_SPI_CLKS_H */ 16#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 6a5fbb534e82..998daf2add92 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -1,46 +1,66 @@
1/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h 1/*
2 * 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * Samsung sysmmu driver for EXYNOS4 5 * EXYNOS - System MMU support
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
11*/ 10 */
12 11
13#ifndef __ASM_ARM_ARCH_SYSMMU_H 12#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ 13#define _ARM_MACH_EXYNOS_SYSMMU_H_
15 14
16enum exynos4_sysmmu_ips { 15struct sysmmu_platform_data {
17 SYSMMU_MDMA, 16 char *dbgname;
18 SYSMMU_SSS, 17 /* comma(,) separated list of clock names for clock gating */
19 SYSMMU_FIMC0, 18 char *clockname;
20 SYSMMU_FIMC1,
21 SYSMMU_FIMC2,
22 SYSMMU_FIMC3,
23 SYSMMU_JPEG,
24 SYSMMU_FIMD0,
25 SYSMMU_FIMD1,
26 SYSMMU_PCIe,
27 SYSMMU_G2D,
28 SYSMMU_ROTATOR,
29 SYSMMU_MDMA2,
30 SYSMMU_TV,
31 SYSMMU_MFC_L,
32 SYSMMU_MFC_R,
33 EXYNOS4_SYSMMU_TOTAL_IPNUM,
34}; 19};
35 20
36#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM 21#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
22
23#define SYSMMU_CLOCK_NAME "sysmmu"
24#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
25
26#ifdef CONFIG_EXYNOS_DEV_SYSMMU
27#include <linux/device.h>
28struct platform_device;
29
30#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
31
32extern struct platform_device SYSMMU_PLATDEV(mfc_l);
33extern struct platform_device SYSMMU_PLATDEV(mfc_r);
34extern struct platform_device SYSMMU_PLATDEV(tv);
35extern struct platform_device SYSMMU_PLATDEV(jpeg);
36extern struct platform_device SYSMMU_PLATDEV(rot);
37extern struct platform_device SYSMMU_PLATDEV(fimc0);
38extern struct platform_device SYSMMU_PLATDEV(fimc1);
39extern struct platform_device SYSMMU_PLATDEV(fimc2);
40extern struct platform_device SYSMMU_PLATDEV(fimc3);
41extern struct platform_device SYSMMU_PLATDEV(gsc0);
42extern struct platform_device SYSMMU_PLATDEV(gsc1);
43extern struct platform_device SYSMMU_PLATDEV(gsc2);
44extern struct platform_device SYSMMU_PLATDEV(gsc3);
45extern struct platform_device SYSMMU_PLATDEV(isp);
46extern struct platform_device SYSMMU_PLATDEV(fimd0);
47extern struct platform_device SYSMMU_PLATDEV(fimd1);
48extern struct platform_device SYSMMU_PLATDEV(camif0);
49extern struct platform_device SYSMMU_PLATDEV(camif1);
50extern struct platform_device SYSMMU_PLATDEV(2d);
37 51
38extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM]; 52#ifdef CONFIG_IOMMU_API
53static inline void platform_set_sysmmu(
54 struct device *sysmmu, struct device *dev)
55{
56 dev->archdata.iommu = sysmmu;
57}
58#endif
39 59
40typedef enum exynos4_sysmmu_ips sysmmu_ips; 60#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
61#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
62#endif
41 63
42void sysmmu_clk_init(struct device *dev, sysmmu_ips ips); 64#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
43void sysmmu_clk_enable(sysmmu_ips ips);
44void sysmmu_clk_disable(sysmmu_ips ips);
45 65
46#endif /* __ASM_ARM_ARCH_SYSMMU_H */ 66#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index d726fcd3acf9..6ce21484501e 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -157,7 +157,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
157 &s3c_device_hsmmc3, 157 &s3c_device_hsmmc3,
158 &s3c_device_rtc, 158 &s3c_device_rtc,
159 &s3c_device_wdt, 159 &s3c_device_wdt,
160 &exynos4_device_sysmmu,
161 &samsung_asoc_dma, 160 &samsung_asoc_dma,
162 &armlex4210_smsc911x, 161 &armlex4210_smsc911x,
163 &exynos4_device_ahci, 162 &exynos4_device_ahci,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 83b91fa777c1..495c7e502be1 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -281,7 +281,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
281 &s5p_device_mfc_l, 281 &s5p_device_mfc_l,
282 &s5p_device_mfc_r, 282 &s5p_device_mfc_r,
283 &exynos4_device_spdif, 283 &exynos4_device_spdif,
284 &exynos4_device_sysmmu,
285 &samsung_asoc_dma, 284 &samsung_asoc_dma,
286 &samsung_asoc_idma, 285 &samsung_asoc_idma,
287 &s5p_device_fimd0, 286 &s5p_device_fimd0,
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb57724..f0bb4677eb11 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
315 315
316 if (soc_is_exynos4212()) { 316 if (soc_is_exynos4212() || soc_is_exynos4412()) {
317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); 317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | 318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
319 S5P_USE_STANDBYWFE_ISP_ARM); 319 S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5c3e8f..77c6815eebee 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
94 { PMU_TABLE_END,}, 94 { PMU_TABLE_END,},
95}; 95};
96 96
97static struct exynos4_pmu_conf exynos4212_pmu_config[] = { 97static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
202 { PMU_TABLE_END,}, 202 { PMU_TABLE_END,},
203}; 203};
204 204
205static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
206 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
207 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
208 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
209 { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
210 { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
211 { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
212 { PMU_TABLE_END,},
213};
214
205void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 215void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
206{ 216{
207 unsigned int i; 217 unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
209 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) 219 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
210 __raw_writel(exynos4_pmu_config[i].val[mode], 220 __raw_writel(exynos4_pmu_config[i].val[mode],
211 exynos4_pmu_config[i].reg); 221 exynos4_pmu_config[i].reg);
222
223 if (soc_is_exynos4412()) {
224 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
225 __raw_writel(exynos4412_pmu_config[i].val[mode],
226 exynos4412_pmu_config[i].reg);
227 }
212} 228}
213 229
214static int __init exynos4_pmu_init(void) 230static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
218 if (soc_is_exynos4210()) { 234 if (soc_is_exynos4210()) {
219 exynos4_pmu_config = exynos4210_pmu_config; 235 exynos4_pmu_config = exynos4210_pmu_config;
220 pr_info("EXYNOS4210 PMU Initialize\n"); 236 pr_info("EXYNOS4210 PMU Initialize\n");
221 } else if (soc_is_exynos4212()) { 237 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
222 exynos4_pmu_config = exynos4212_pmu_config; 238 exynos4_pmu_config = exynos4x12_pmu_config;
223 pr_info("EXYNOS4212 PMU Initialize\n"); 239 pr_info("EXYNOS4x12 PMU Initialize\n");
224 } else { 240 } else {
225 pr_info("EXYNOS4: PMU not supported\n"); 241 pr_info("EXYNOS4: PMU not supported\n");
226 } 242 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-13 23:51:44 -0500