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authorKukjin Kim <kgene.kim@samsung.com>2011-02-14 00:59:52 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-02-21 23:51:15 -0500
commitd11135ca4f6e626e1c8aa78de6d472a11a9e9811 (patch)
treeeb87118113748099879294e33835c5f8304949a9 /arch/arm/mach-exynos4
parent3db3ae5eb94eb8579991174fe66999261b66018d (diff)
ARM: EXYNOS4: Moved board support files
This patch moves board support files, SMDKC210, SMKDV310 and UNIVERSAL_C210 into arch/arm/mach-exynos4/ according to the change of ARCH name, EXYNOS4. Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c223
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c224
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c237
3 files changed, 684 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
new file mode 100644
index 000000000000..25a256818122
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -0,0 +1,223 @@
1/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach-types.h>
21
22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
24#include <plat/exynos4.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
30
31#include <mach/map.h>
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = SMDKC210_UCON_DEFAULT,
52 .ulcon = SMDKC210_ULCON_DEFAULT,
53 .ufcon = SMDKC210_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = SMDKC210_UCON_DEFAULT,
59 .ulcon = SMDKC210_ULCON_DEFAULT,
60 .ufcon = SMDKC210_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = SMDKC210_UCON_DEFAULT,
66 .ulcon = SMDKC210_ULCON_DEFAULT,
67 .ufcon = SMDKC210_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = SMDKC210_UCON_DEFAULT,
73 .ulcon = SMDKC210_ULCON_DEFAULT,
74 .ufcon = SMDKC210_UFCON_DEFAULT,
75 },
76};
77
78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif
87};
88
89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94};
95
96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif
105};
106
107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112};
113
114static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = {
116 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_EINT(5),
122 .end = IRQ_EINT(5),
123 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
124 },
125};
126
127static struct smsc911x_platform_config smsc9215_config = {
128 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
131 .phy_interface = PHY_INTERFACE_MODE_MII,
132 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
133};
134
135static struct platform_device smdkc210_smsc911x = {
136 .name = "smsc911x",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
139 .resource = smdkc210_smsc911x_resources,
140 .dev = {
141 .platform_data = &smsc9215_config,
142 },
143};
144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
149static struct platform_device *smdkc210_devices[] __initdata = {
150 &s3c_device_hsmmc0,
151 &s3c_device_hsmmc1,
152 &s3c_device_hsmmc2,
153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
155 &s3c_device_rtc,
156 &s3c_device_wdt,
157 &exynos4_device_ac97,
158 &exynos4_device_i2s0,
159 &exynos4_device_pd[PD_MFC],
160 &exynos4_device_pd[PD_G3D],
161 &exynos4_device_pd[PD_LCD0],
162 &exynos4_device_pd[PD_LCD1],
163 &exynos4_device_pd[PD_CAM],
164 &exynos4_device_pd[PD_TV],
165 &exynos4_device_pd[PD_GPS],
166 &exynos4_device_sysmmu,
167 &samsung_asoc_dma,
168 &smdkc210_smsc911x,
169};
170
171static void __init smdkc210_smsc911x_init(void)
172{
173 u32 cs1;
174
175 /* configure nCS1 width to 16 bits */
176 cs1 = __raw_readl(S5P_SROM_BW) &
177 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
178 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
179 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
180 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
181 S5P_SROM_BW__NCS1__SHIFT;
182 __raw_writel(cs1, S5P_SROM_BW);
183
184 /* set timing for nCS1 suitable for ethernet chip */
185 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
186 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
187 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
188 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
189 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
190 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
191 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
192}
193
194static void __init smdkc210_map_io(void)
195{
196 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
197 s3c24xx_init_clocks(24000000);
198 s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
199}
200
201static void __init smdkc210_machine_init(void)
202{
203 s3c_i2c1_set_platdata(NULL);
204 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
205
206 smdkc210_smsc911x_init();
207
208 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
209 s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
210 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
212
213 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
214}
215
216MACHINE_START(SMDKC210, "SMDKC210")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 .boot_params = S5P_PA_SDRAM + 0x100,
219 .init_irq = exynos4_init_irq,
220 .map_io = smdkc210_map_io,
221 .init_machine = smdkc210_machine_init,
222 .timer = &exynos4_timer,
223MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
new file mode 100644
index 000000000000..07860a5b2f5d
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -0,0 +1,224 @@
1/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach-types.h>
21
22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
24#include <plat/exynos4.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
30
31#include <mach/map.h>
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = SMDKV310_UCON_DEFAULT,
52 .ulcon = SMDKV310_ULCON_DEFAULT,
53 .ufcon = SMDKV310_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = SMDKV310_UCON_DEFAULT,
59 .ulcon = SMDKV310_ULCON_DEFAULT,
60 .ufcon = SMDKV310_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = SMDKV310_UCON_DEFAULT,
66 .ulcon = SMDKV310_ULCON_DEFAULT,
67 .ufcon = SMDKV310_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = SMDKV310_UCON_DEFAULT,
73 .ulcon = SMDKV310_ULCON_DEFAULT,
74 .ufcon = SMDKV310_UFCON_DEFAULT,
75 },
76};
77
78static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif
87};
88
89static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94};
95
96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif
105};
106
107static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112};
113
114static struct resource smdkv310_smsc911x_resources[] = {
115 [0] = {
116 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_EINT(5),
122 .end = IRQ_EINT(5),
123 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
124 },
125};
126
127static struct smsc911x_platform_config smsc9215_config = {
128 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
131 .phy_interface = PHY_INTERFACE_MODE_MII,
132 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
133};
134
135static struct platform_device smdkv310_smsc911x = {
136 .name = "smsc911x",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
139 .resource = smdkv310_smsc911x_resources,
140 .dev = {
141 .platform_data = &smsc9215_config,
142 },
143};
144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
149static struct platform_device *smdkv310_devices[] __initdata = {
150 &s3c_device_hsmmc0,
151 &s3c_device_hsmmc1,
152 &s3c_device_hsmmc2,
153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
155 &s3c_device_rtc,
156 &s3c_device_wdt,
157 &exynos4_device_ac97,
158 &exynos4_device_i2s0,
159 &exynos4_device_pd[PD_MFC],
160 &exynos4_device_pd[PD_G3D],
161 &exynos4_device_pd[PD_LCD0],
162 &exynos4_device_pd[PD_LCD1],
163 &exynos4_device_pd[PD_CAM],
164 &exynos4_device_pd[PD_TV],
165 &exynos4_device_pd[PD_GPS],
166 &exynos4_device_sysmmu,
167 &samsung_asoc_dma,
168 &smdkv310_smsc911x,
169};
170
171static void __init smdkv310_smsc911x_init(void)
172{
173 u32 cs1;
174
175 /* configure nCS1 width to 16 bits */
176 cs1 = __raw_readl(S5P_SROM_BW) &
177 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
178 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
179 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
180 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
181 S5P_SROM_BW__NCS1__SHIFT;
182 __raw_writel(cs1, S5P_SROM_BW);
183
184 /* set timing for nCS1 suitable for ethernet chip */
185 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
186 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
187 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
188 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
189 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
190 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
191 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
192}
193
194static void __init smdkv310_map_io(void)
195{
196 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
197 s3c24xx_init_clocks(24000000);
198 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
199}
200
201static void __init smdkv310_machine_init(void)
202{
203 s3c_i2c1_set_platdata(NULL);
204 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
205
206 smdkv310_smsc911x_init();
207
208 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
209 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
210 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
212
213 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
214}
215
216MACHINE_START(SMDKV310, "SMDKV310")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
219 .boot_params = S5P_PA_SDRAM + 0x100,
220 .init_irq = exynos4_init_irq,
221 .map_io = smdkv310_map_io,
222 .init_machine = smdkv310_machine_init,
223 .timer = &exynos4_timer,
224MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
new file mode 100644
index 000000000000..b22b6ef2a94b
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -0,0 +1,237 @@
1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach-types.h>
22
23#include <plat/regs-serial.h>
24#include <plat/exynos4.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG256 | \
43 S5PV210_UFCON_RXTRIG256)
44
45static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .ucon = UNIVERSAL_UCON_DEFAULT,
49 .ulcon = UNIVERSAL_ULCON_DEFAULT,
50 .ufcon = UNIVERSAL_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .ucon = UNIVERSAL_UCON_DEFAULT,
55 .ulcon = UNIVERSAL_ULCON_DEFAULT,
56 .ufcon = UNIVERSAL_UFCON_DEFAULT,
57 },
58 [2] = {
59 .hwport = 2,
60 .ucon = UNIVERSAL_UCON_DEFAULT,
61 .ulcon = UNIVERSAL_ULCON_DEFAULT,
62 .ufcon = UNIVERSAL_UFCON_DEFAULT,
63 },
64 [3] = {
65 .hwport = 3,
66 .ucon = UNIVERSAL_UCON_DEFAULT,
67 .ulcon = UNIVERSAL_ULCON_DEFAULT,
68 .ufcon = UNIVERSAL_UFCON_DEFAULT,
69 },
70};
71
72static struct gpio_keys_button universal_gpio_keys_tables[] = {
73 {
74 .code = KEY_VOLUMEUP,
75 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
76 .desc = "gpio-keys: KEY_VOLUMEUP",
77 .type = EV_KEY,
78 .active_low = 1,
79 .debounce_interval = 1,
80 }, {
81 .code = KEY_VOLUMEDOWN,
82 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
83 .desc = "gpio-keys: KEY_VOLUMEDOWN",
84 .type = EV_KEY,
85 .active_low = 1,
86 .debounce_interval = 1,
87 }, {
88 .code = KEY_CONFIG,
89 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
90 .desc = "gpio-keys: KEY_CONFIG",
91 .type = EV_KEY,
92 .active_low = 1,
93 .debounce_interval = 1,
94 }, {
95 .code = KEY_CAMERA,
96 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
97 .desc = "gpio-keys: KEY_CAMERA",
98 .type = EV_KEY,
99 .active_low = 1,
100 .debounce_interval = 1,
101 }, {
102 .code = KEY_OK,
103 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
104 .desc = "gpio-keys: KEY_OK",
105 .type = EV_KEY,
106 .active_low = 1,
107 .debounce_interval = 1,
108 },
109};
110
111static struct gpio_keys_platform_data universal_gpio_keys_data = {
112 .buttons = universal_gpio_keys_tables,
113 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
114};
115
116static struct platform_device universal_gpio_keys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &universal_gpio_keys_data,
120 },
121};
122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = EXYNOS4_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
190/* I2C0 */
191static struct i2c_board_info i2c0_devs[] __initdata = {
192 /* Camera, To be updated */
193};
194
195/* I2C1 */
196static struct i2c_board_info i2c1_devs[] __initdata = {
197 /* Gyro, To be updated */
198};
199
200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
208 &universal_gpio_keys,
209 &s5p_device_onenand,
210};
211
212static void __init universal_map_io(void)
213{
214 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
215 s3c24xx_init_clocks(24000000);
216 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
217}
218
219static void __init universal_machine_init(void)
220{
221 universal_sdhci_init();
222
223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
225
226 /* Last */
227 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
228}
229
230MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
231 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
232 .boot_params = S5P_PA_SDRAM + 0x100,
233 .init_irq = exynos4_init_irq,
234 .map_io = universal_map_io,
235 .init_machine = universal_machine_init,
236 .timer = &exynos4_timer,
237MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-11 12:30:38 -0400