diff options
author | Marek Szyprowski <m.szyprowski@samsung.com> | 2011-03-15 08:17:43 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-03-15 08:17:43 -0400 |
commit | 721bbd4a06e83995ac1679d9cdca19a608fb0122 (patch) | |
tree | 5e2612cdade5348607e2de8e87f1a056c0e6f142 /arch/arm/mach-exynos4 | |
parent | a43efddc3bf8b143ff9352763cd39d425db14d27 (diff) |
ARM: EXYNOS4: Add support for gpio interrupts
This patch adds support for gpio interrupts on Samsung EXYNOS4 platform.
Common s5p-gpioint.c code is used for handling gpio interrupts. Each gpio
line that needs gpio interrupt support must be later registered with
s5p_register_gpio_interrupt() function.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r-- | arch/arm/mach-exynos4/gpiolib.c | 18 | ||||
-rw-r--r-- | arch/arm/mach-exynos4/include/mach/irqs.h | 12 |
2 files changed, 25 insertions, 5 deletions
diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c index 1b4121c2e53e..d54ca6adb660 100644 --- a/arch/arm/mach-exynos4/gpiolib.c +++ b/arch/arm/mach-exynos4/gpiolib.c | |||
@@ -304,6 +304,7 @@ static __init int exynos4_gpiolib_init(void) | |||
304 | { | 304 | { |
305 | struct s3c_gpio_chip *chip; | 305 | struct s3c_gpio_chip *chip; |
306 | int i; | 306 | int i; |
307 | int group = 0; | ||
307 | int nr_chips; | 308 | int nr_chips; |
308 | 309 | ||
309 | /* GPIO part 1 */ | 310 | /* GPIO part 1 */ |
@@ -312,8 +313,11 @@ static __init int exynos4_gpiolib_init(void) | |||
312 | nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit); | 313 | nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit); |
313 | 314 | ||
314 | for (i = 0; i < nr_chips; i++, chip++) { | 315 | for (i = 0; i < nr_chips; i++, chip++) { |
315 | if (chip->config == NULL) | 316 | if (chip->config == NULL) { |
316 | chip->config = &gpio_cfg; | 317 | chip->config = &gpio_cfg; |
318 | /* Assign the GPIO interrupt group */ | ||
319 | chip->group = group++; | ||
320 | } | ||
317 | if (chip->base == NULL) | 321 | if (chip->base == NULL) |
318 | chip->base = S5P_VA_GPIO1 + (i) * 0x20; | 322 | chip->base = S5P_VA_GPIO1 + (i) * 0x20; |
319 | } | 323 | } |
@@ -326,8 +330,11 @@ static __init int exynos4_gpiolib_init(void) | |||
326 | nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit); | 330 | nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit); |
327 | 331 | ||
328 | for (i = 0; i < nr_chips; i++, chip++) { | 332 | for (i = 0; i < nr_chips; i++, chip++) { |
329 | if (chip->config == NULL) | 333 | if (chip->config == NULL) { |
330 | chip->config = &gpio_cfg; | 334 | chip->config = &gpio_cfg; |
335 | /* Assign the GPIO interrupt group */ | ||
336 | chip->group = group++; | ||
337 | } | ||
331 | if (chip->base == NULL) | 338 | if (chip->base == NULL) |
332 | chip->base = S5P_VA_GPIO2 + (i) * 0x20; | 339 | chip->base = S5P_VA_GPIO2 + (i) * 0x20; |
333 | } | 340 | } |
@@ -340,13 +347,18 @@ static __init int exynos4_gpiolib_init(void) | |||
340 | nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit); | 347 | nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit); |
341 | 348 | ||
342 | for (i = 0; i < nr_chips; i++, chip++) { | 349 | for (i = 0; i < nr_chips; i++, chip++) { |
343 | if (chip->config == NULL) | 350 | if (chip->config == NULL) { |
344 | chip->config = &gpio_cfg; | 351 | chip->config = &gpio_cfg; |
352 | /* Assign the GPIO interrupt group */ | ||
353 | chip->group = group++; | ||
354 | } | ||
345 | if (chip->base == NULL) | 355 | if (chip->base == NULL) |
346 | chip->base = S5P_VA_GPIO3 + (i) * 0x20; | 356 | chip->base = S5P_VA_GPIO3 + (i) * 0x20; |
347 | } | 357 | } |
348 | 358 | ||
349 | samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips); | 359 | samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips); |
360 | s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); | ||
361 | s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); | ||
350 | 362 | ||
351 | return 0; | 363 | return 0; |
352 | } | 364 | } |
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h index 1db1de8e3e81..5d037301d21a 100644 --- a/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/arch/arm/mach-exynos4/include/mach/irqs.h | |||
@@ -85,6 +85,9 @@ | |||
85 | #define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) | 85 | #define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) |
86 | #define IRQ_RTC_TIC COMBINER_IRQ(23, 1) | 86 | #define IRQ_RTC_TIC COMBINER_IRQ(23, 1) |
87 | 87 | ||
88 | #define IRQ_GPIO_XB COMBINER_IRQ(24, 0) | ||
89 | #define IRQ_GPIO_XA COMBINER_IRQ(24, 1) | ||
90 | |||
88 | #define IRQ_UART0 COMBINER_IRQ(26, 0) | 91 | #define IRQ_UART0 COMBINER_IRQ(26, 0) |
89 | #define IRQ_UART1 COMBINER_IRQ(26, 1) | 92 | #define IRQ_UART1 COMBINER_IRQ(26, 1) |
90 | #define IRQ_UART2 COMBINER_IRQ(26, 2) | 93 | #define IRQ_UART2 COMBINER_IRQ(26, 2) |
@@ -145,8 +148,13 @@ | |||
145 | #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) | 148 | #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) |
146 | #define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) | 149 | #define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) |
147 | 150 | ||
148 | /* Set the default NR_IRQS */ | 151 | /* optional GPIO interrupts */ |
152 | #define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32) | ||
153 | #define IRQ_GPIO1_NR_GROUPS 16 | ||
154 | #define IRQ_GPIO2_NR_GROUPS 9 | ||
155 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) | ||
149 | 156 | ||
150 | #define NR_IRQS (S5P_IRQ_EINT_BASE + 32) | 157 | /* Set the default NR_IRQS */ |
158 | #define NR_IRQS (IRQ_GPIO_END) | ||
151 | 159 | ||
152 | #endif /* __ASM_ARCH_IRQS_H */ | 160 | #endif /* __ASM_ARCH_IRQS_H */ |