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authorKukjin Kim <kgene.kim@samsung.com>2011-09-16 03:38:43 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-09-16 03:38:43 -0400
commitbe6bb8cc8d2bd033a1f89983f2f13bdb3548a08f (patch)
tree2b7f76cc2154e5589a605f97a663c8afe4f6016f /arch/arm/mach-exynos4
parentd03c35939d2a447093e60133156217d6512aa9e3 (diff)
parentb02b5da4d15d7f7a250888d003121e1b5b69d00b (diff)
Merge branch 'next/topic-cpuid-rev' into next/topic-add-exynos4212
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/cpu.c28
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos4/platsmp.c8
3 files changed, 31 insertions, 8 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397..0d281bbe345a 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -44,11 +44,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
44 .length = SZ_4K, 44 .length = SZ_4K,
45 .type = MT_DEVICE, 45 .type = MT_DEVICE,
46 }, { 46 }, {
47 .virtual = (unsigned long)S5P_VA_SYSRAM,
48 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
49 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)S5P_VA_CMU, 47 .virtual = (unsigned long)S5P_VA_CMU,
53 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 48 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
54 .length = SZ_128K, 49 .length = SZ_128K,
@@ -121,6 +116,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
121 }, 116 },
122}; 117};
123 118
119static struct map_desc exynos4_iodesc0[] __initdata = {
120 {
121 .virtual = (unsigned long)S5P_VA_SYSRAM,
122 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
123 .length = SZ_4K,
124 .type = MT_DEVICE,
125 },
126};
127
128static struct map_desc exynos4_iodesc1[] __initdata = {
129 {
130 .virtual = (unsigned long)S5P_VA_SYSRAM,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 },
135};
136
124static void exynos4_idle(void) 137static void exynos4_idle(void)
125{ 138{
126 if (!need_resched()) 139 if (!need_resched())
@@ -143,6 +156,11 @@ void __init exynos4_map_io(void)
143{ 156{
144 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 157 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
145 158
159 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
160 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
161 else
162 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
163
146 /* initialize device information early */ 164 /* initialize device information early */
147 exynos4_default_sdhci0(); 165 exynos4_default_sdhci0();
148 exynos4_default_sdhci1(); 166 exynos4_default_sdhci1();
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e2..7073ac730855 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define EXYNOS4_PA_SYSRAM 0x02020000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
27 28
28#define EXYNOS4_PA_FIMC0 0x11800000 29#define EXYNOS4_PA_FIMC0 0x11800000
29#define EXYNOS4_PA_FIMC1 0x11810000 30#define EXYNOS4_PA_FIMC1 0x11810000
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index df6ef1b2f98b..a3346e36d0ae 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,12 @@
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 31#include <mach/regs-pmu.h>
32 32
33#include <plat/cpu.h>
34
33extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
34 36
35#define CPU1_BOOT_REG S5P_VA_SYSRAM 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
38 S5P_INFORM5 : S5P_VA_SYSRAM)
36 39
37/* 40/*
38 * control for which core is the next to come out of the secondary 41 * control for which core is the next to come out of the secondary
@@ -218,5 +221,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
218 * until it receives a soft interrupt, and then the 221 * until it receives a soft interrupt, and then the
219 * secondary CPU branches to this address. 222 * secondary CPU branches to this address.
220 */ 223 */
221 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); 224 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
225 CPU1_BOOT_REG);
222} 226}