ARM: EXYNOS4: Add support new EXYNOS4212 SoC

This patch adds Samsung EXYNOS4212 SoC support.
The EXYNOS4212 integrates a ARM Cortex A9 multi-core.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

3 files changed, 14 insertions, 3 deletions

diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index bee8f77de2ab..0b40289d4f73 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -15,6 +15,11 @@ config CPU_EXYNOS4210
         help
           Enable EXYNOS4210 CPU support
 
+config SOC_EXYNOS4212
+        bool
+        help
+          Enable EXYNOS4212 SoC support
+
 config EXYNOS4_MCT
         bool
         default y
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e3e93ea41385..46244576452a 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj-				:=
 
 # Core support for EXYNOS4 system
 
-obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
 obj-$(CONFIG_PM)                += pm.o sleep.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0d281bbe345a..1e1a7a9d2ae7 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -241,7 +241,11 @@ static int __init exynos4_l2x0_cache_init(void)
 {
         /* TAG, Data Latency Control: 2cycle */
         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+        if (soc_is_exynos4210())
+                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        else if (soc_is_exynos4212())
+                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 
         /* L2X0 Prefetch Control */
         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);