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authorSylwester Nawrocki <s.nawrocki@samsung.com>2011-03-10 07:53:40 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-03-11 01:49:01 -0500
commit1d45ac49daa15fd0a64c58744ac9ea6451e607e6 (patch)
tree8db8bb0dd987dfd3c4a166893040de29ba9482e9 /arch/arm/mach-exynos4
parente24d208de6bc779c6bd97523cde2665a33f2be4d (diff)
ARM: S5P: Add support for common MIPI CSIS/DSIM D-PHY control
Add common code for MIPI-CSIS and MIPI-DSIM drivers to support their corresponding D-PHY's enable and reset control. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h4
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h5
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index ba8f91c04e19..38dee94fc7ae 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -160,7 +160,9 @@
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162 162
163/* Compatibility defines */ 163/* Compatibility defines and inclusion */
164
165#include <mach/regs-pmu.h>
164 166
165#define S5P_EPLL_CON S5P_EPLL_CON0 167#define S5P_EPLL_CON S5P_EPLL_CON0
166 168
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index 2ddd6175dfa0..985416d1085f 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -17,6 +17,11 @@
17 17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19 19
20#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
21#define S5P_MIPI_DPHY_ENABLE (1 << 0)
22#define S5P_MIPI_DPHY_SRESETN (1 << 1)
23#define S5P_MIPI_DPHY_MRESETN (1 << 2)
24
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) 25#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) 26#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 27#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)