ARM: EXYNOS4: Add support Core1 Power On/Off with hotplug in/out

To insert the code for power on/off with pmu control to support hotplug in/out core1
As for hotplug.c, the codes for core1 to be hotplug in/out is inserted.
As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined.
As for platsmp.c, the codes for core1 to be powered on is inserted.

Signed-off-by: JungHi Min <junghi.min@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 29 insertions, 1 deletions

diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index a79863cb7f79..a7f312c12893 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
 
 extern void exynos4_secondary_startup(void);
 
+#define CPU1_BOOT_REG S5P_VA_SYSRAM
+
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
@@ -125,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         write_pen_release(cpu);
 
+        if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+                __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                             S5P_ARM_CORE1_CONFIGURATION);
+
+                timeout = 10;
+
+                /* wait max 10 ms until cpu1 is on */
+                while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                        & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+                        if (timeout-- == 0)
+                                break;
+
+                        mdelay(1);
+                }
+
+                if (timeout == 0) {
+                        printk(KERN_ERR "cpu1 power enable failed");
+                        spin_unlock(&boot_lock);
+                        return -ETIMEDOUT;
+                }
+        }
         /*
          * Send the secondary CPU a soft interrupt, thereby causing
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
                 smp_rmb();
+
+                __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                        CPU1_BOOT_REG);
+                gic_raise_softirq(cpumask_of(cpu), 1);
+
                 if (pen_release == -1)
                         break;