Merge branch 'next-samsung-devel' into next-samsung-devel-2

Conflicts:
	arch/arm/mach-exynos4/clock.c
	arch/arm/mach-s3c2412/gpio.c
	arch/arm/mach-s5p64x0/dma.c
	arch/arm/mach-s5p64x0/gpiolib.c

7 files changed, 111 insertions, 14 deletions

diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..201842a3769e 100644
--- a/arch/arm/mach-exynos4/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_DMA_H
 #define __MACH_DMA_H
 
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
+/* This platform uses the common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
 
 #endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
new file mode 100644
index 000000000000..9dbe3179ad59
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series i2c hdmiphy helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_I2C_HDMIPHY_H_
+#define PLAT_S5P_I2C_HDMIPHY_H_
+
+#define S5P_I2C_HDMIPHY_BUS_NUM         (8)
+
+#endif
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f3757..62093b9339db 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -93,7 +93,11 @@
 #define IRQ_2D                  IRQ_SPI(89)
 #define IRQ_PCIE                IRQ_SPI(90)
 
+#define IRQ_MIXER               IRQ_SPI(91)
+#define IRQ_HDMI                IRQ_SPI(92)
+#define IRQ_IIC_HDMIPHY         IRQ_SPI(93)
 #define IRQ_MFC                 IRQ_SPI(94)
+#define IRQ_SDO                 IRQ_SPI(95)
 
 #define IRQ_AUDIO_SS            IRQ_SPI(96)
 #define IRQ_I2S0                IRQ_SPI(97)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 7073ac730855..1bea7d139bb0 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -113,6 +113,12 @@
 
 #define EXYNOS4_PA_UART                 0x13800000
 
+#define EXYNOS4_PA_VP                   0x12C00000
+#define EXYNOS4_PA_MIXER                0x12C10000
+#define EXYNOS4_PA_SDO                  0x12C20000
+#define EXYNOS4_PA_HDMI                 0x12D00000
+#define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
+
 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC                  0x13910000
@@ -162,6 +168,12 @@
 #define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 
+#define S5P_PA_SDO                      EXYNOS4_PA_SDO
+#define S5P_PA_VP                       EXYNOS4_PA_VP
+#define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
+#define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
+#define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
+
 #define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
 
 /* UART */
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index 1df3b81f96e8..9d8da51e35ca 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -14,6 +14,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+
+#ifndef __ASM_ARCH_PM_CORE_H
+#define __ASM_ARCH_PM_CORE_H __FILE__
+
 #include <mach/regs-pmu.h>
 
 static inline void s3c_pm_debug_init_uart(void)
@@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
         /* nothing here yet */
 }
 
-static inline void s3c_pm_saved_gpios(void)
+static inline void samsung_pm_saved_gpios(void)
 {
         /* nothing here yet */
 }
+
+#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
index a952904b010e..632dd5630138 100644
--- a/arch/arm/mach-exynos4/include/mach/pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_PMU_H
 #define __ASM_ARCH_PMU_H __FILE__
 
+#define PMU_TABLE_END   NULL
+
 enum sys_powerdown {
         SYS_AFTR,
         SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
         NUM_SYS_POWERDOWN,
 };
 
+struct exynos4_pmu_conf {
+        void __iomem *reg;
+        unsigned int val[NUM_SYS_POWERDOWN];
+};
+
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
 
 #endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index cdf9b47c303c..4fff8e938fec 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -25,9 +25,10 @@
 
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
 #define S5P_USE_STANDBY_WFI1                    (1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM              (1 << 18)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
 #define S5P_USE_STANDBY_WFE1                    (1 << 25)
-#define S5P_USE_MASK                            ((0x3 << 16) | (0x3 << 24))
+#define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
 
@@ -35,15 +36,17 @@
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
 #define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
 
-#define S5P_USBHOST_PHY_CONTROL                 S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE                  (1 << 0)
+#define S5P_HDMI_PHY_CONTROL                    S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE                     (1 << 0)
+
+#define S5P_DAC_PHY_CONTROL                     S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE                      (1 << 0)
 
 #define S5P_MIPI_DPHY_CONTROL(n)                S5P_PMUREG(0x0710 + (n) * 4)
 #define S5P_MIPI_DPHY_ENABLE                    (1 << 0)
 #define S5P_MIPI_DPHY_SRESETN                   (1 << 1)
 #define S5P_MIPI_DPHY_MRESETN                   (1 << 2)
 
-#define S5P_PMU_SATA_PHY_CONTROL                S5P_PMUREG(0x0720)
 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
 #define S5P_INFORM2                             S5P_PMUREG(0x0808)
@@ -76,7 +79,6 @@
 #define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
 #define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR             S5P_PMUREG(0x1154)
 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
 #define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
 #define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
@@ -84,7 +86,6 @@
 #define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
 #define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
 #define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_LCD1_LOWPWR               S5P_PMUREG(0x1174)
 #define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
 #define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
 #define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
@@ -92,14 +93,11 @@
 #define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
 #define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
 #define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
-#define S5P_MODIMIF_MEM_LOWPWR                  S5P_PMUREG(0x11C4)
 #define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
 #define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
 #define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
 #define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
 #define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
-#define S5P_PCIE_MEM_LOWPWR                     S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR                     S5P_PMUREG(0x11E4)
 #define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
 #define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
@@ -120,7 +118,6 @@
 #define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
 #define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
 #define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
-#define S5P_LCD1_LOWPWR                         S5P_PMUREG(0x1394)
 #define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
@@ -156,7 +153,6 @@
 #define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
 #define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
 #define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF                       S5P_PMUREG(0x3CA0)
 #define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
@@ -165,4 +161,60 @@
 
 #define S5P_CHECK_SLEEP                         0x00000BAD
 
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE          (1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL        S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR             S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR            S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR              S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR              S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR                S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR              S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR        S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR              S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR                  S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR          S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR          S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR                      S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR                  S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR        S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR            S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR                S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR            S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR                          S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR               S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR                S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR               S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR               S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION                     S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION                     S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION                  S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION                      S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION                  S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION                   S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION                    S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION                    S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */