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authorThomas Abraham <thomas.ab@samsung.com>2011-06-14 06:12:27 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 13:03:25 -0400
commitbadc4f2d604ac20489a363b918edb0241b3b9032 (patch)
tree012ce763b0737c61a81d3d8f2527e54d7d092df9 /arch/arm/mach-exynos4/clock.c
parentb2a9dd466cb3a7c0122c644a4c6c112b424ca011 (diff)
ARM: EXYNOS4: Add clkdev support
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [kgene.kim@samsung.com: removed changes of mach-exynos4/time.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/clock.c')
-rw-r--r--arch/arm/mach-exynos4/clock.c177
1 files changed, 57 insertions, 120 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d508fde..98b5cc4a9b20 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
27 27
28static struct clk clk_sclk_hdmi27m = { 28static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 29 .name = "sclk_hdmi27m",
30 .id = -1,
31 .rate = 27000000, 30 .rate = 27000000,
32}; 31};
33 32
34static struct clk clk_sclk_hdmiphy = { 33static struct clk clk_sclk_hdmiphy = {
35 .name = "sclk_hdmiphy", 34 .name = "sclk_hdmiphy",
36 .id = -1,
37}; 35};
38 36
39static struct clk clk_sclk_usbphy0 = { 37static struct clk clk_sclk_usbphy0 = {
40 .name = "sclk_usbphy0", 38 .name = "sclk_usbphy0",
41 .id = -1,
42 .rate = 27000000, 39 .rate = 27000000,
43}; 40};
44 41
45static struct clk clk_sclk_usbphy1 = { 42static struct clk clk_sclk_usbphy1 = {
46 .name = "sclk_usbphy1", 43 .name = "sclk_usbphy1",
47 .id = -1,
48}; 44};
49 45
50static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 46static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
132static struct clksrc_clk clk_mout_apll = { 128static struct clksrc_clk clk_mout_apll = {
133 .clk = { 129 .clk = {
134 .name = "mout_apll", 130 .name = "mout_apll",
135 .id = -1,
136 }, 131 },
137 .sources = &clk_src_apll, 132 .sources = &clk_src_apll,
138 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
141static struct clksrc_clk clk_sclk_apll = { 136static struct clksrc_clk clk_sclk_apll = {
142 .clk = { 137 .clk = {
143 .name = "sclk_apll", 138 .name = "sclk_apll",
144 .id = -1,
145 .parent = &clk_mout_apll.clk, 139 .parent = &clk_mout_apll.clk,
146 }, 140 },
147 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
150static struct clksrc_clk clk_mout_epll = { 144static struct clksrc_clk clk_mout_epll = {
151 .clk = { 145 .clk = {
152 .name = "mout_epll", 146 .name = "mout_epll",
153 .id = -1,
154 }, 147 },
155 .sources = &clk_src_epll, 148 .sources = &clk_src_epll,
156 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
159static struct clksrc_clk clk_mout_mpll = { 152static struct clksrc_clk clk_mout_mpll = {
160 .clk = { 153 .clk = {
161 .name = "mout_mpll", 154 .name = "mout_mpll",
162 .id = -1,
163 }, 155 },
164 .sources = &clk_src_mpll, 156 .sources = &clk_src_mpll,
165 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
178static struct clksrc_clk clk_moutcore = { 170static struct clksrc_clk clk_moutcore = {
179 .clk = { 171 .clk = {
180 .name = "moutcore", 172 .name = "moutcore",
181 .id = -1,
182 }, 173 },
183 .sources = &clkset_moutcore, 174 .sources = &clkset_moutcore,
184 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 175 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
187static struct clksrc_clk clk_coreclk = { 178static struct clksrc_clk clk_coreclk = {
188 .clk = { 179 .clk = {
189 .name = "core_clk", 180 .name = "core_clk",
190 .id = -1,
191 .parent = &clk_moutcore.clk, 181 .parent = &clk_moutcore.clk,
192 }, 182 },
193 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 183 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
196static struct clksrc_clk clk_armclk = { 186static struct clksrc_clk clk_armclk = {
197 .clk = { 187 .clk = {
198 .name = "armclk", 188 .name = "armclk",
199 .id = -1,
200 .parent = &clk_coreclk.clk, 189 .parent = &clk_coreclk.clk,
201 }, 190 },
202}; 191};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
204static struct clksrc_clk clk_aclk_corem0 = { 193static struct clksrc_clk clk_aclk_corem0 = {
205 .clk = { 194 .clk = {
206 .name = "aclk_corem0", 195 .name = "aclk_corem0",
207 .id = -1,
208 .parent = &clk_coreclk.clk, 196 .parent = &clk_coreclk.clk,
209 }, 197 },
210 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 198 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
213static struct clksrc_clk clk_aclk_cores = { 201static struct clksrc_clk clk_aclk_cores = {
214 .clk = { 202 .clk = {
215 .name = "aclk_cores", 203 .name = "aclk_cores",
216 .id = -1,
217 .parent = &clk_coreclk.clk, 204 .parent = &clk_coreclk.clk,
218 }, 205 },
219 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 206 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
222static struct clksrc_clk clk_aclk_corem1 = { 209static struct clksrc_clk clk_aclk_corem1 = {
223 .clk = { 210 .clk = {
224 .name = "aclk_corem1", 211 .name = "aclk_corem1",
225 .id = -1,
226 .parent = &clk_coreclk.clk, 212 .parent = &clk_coreclk.clk,
227 }, 213 },
228 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 214 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
231static struct clksrc_clk clk_periphclk = { 217static struct clksrc_clk clk_periphclk = {
232 .clk = { 218 .clk = {
233 .name = "periphclk", 219 .name = "periphclk",
234 .id = -1,
235 .parent = &clk_coreclk.clk, 220 .parent = &clk_coreclk.clk,
236 }, 221 },
237 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 222 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
252static struct clksrc_clk clk_mout_corebus = { 237static struct clksrc_clk clk_mout_corebus = {
253 .clk = { 238 .clk = {
254 .name = "mout_corebus", 239 .name = "mout_corebus",
255 .id = -1,
256 }, 240 },
257 .sources = &clkset_mout_corebus, 241 .sources = &clkset_mout_corebus,
258 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 242 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
261static struct clksrc_clk clk_sclk_dmc = { 245static struct clksrc_clk clk_sclk_dmc = {
262 .clk = { 246 .clk = {
263 .name = "sclk_dmc", 247 .name = "sclk_dmc",
264 .id = -1,
265 .parent = &clk_mout_corebus.clk, 248 .parent = &clk_mout_corebus.clk,
266 }, 249 },
267 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 250 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
270static struct clksrc_clk clk_aclk_cored = { 253static struct clksrc_clk clk_aclk_cored = {
271 .clk = { 254 .clk = {
272 .name = "aclk_cored", 255 .name = "aclk_cored",
273 .id = -1,
274 .parent = &clk_sclk_dmc.clk, 256 .parent = &clk_sclk_dmc.clk,
275 }, 257 },
276 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 258 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
279static struct clksrc_clk clk_aclk_corep = { 261static struct clksrc_clk clk_aclk_corep = {
280 .clk = { 262 .clk = {
281 .name = "aclk_corep", 263 .name = "aclk_corep",
282 .id = -1,
283 .parent = &clk_aclk_cored.clk, 264 .parent = &clk_aclk_cored.clk,
284 }, 265 },
285 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 266 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
288static struct clksrc_clk clk_aclk_acp = { 269static struct clksrc_clk clk_aclk_acp = {
289 .clk = { 270 .clk = {
290 .name = "aclk_acp", 271 .name = "aclk_acp",
291 .id = -1,
292 .parent = &clk_mout_corebus.clk, 272 .parent = &clk_mout_corebus.clk,
293 }, 273 },
294 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
297static struct clksrc_clk clk_pclk_acp = { 277static struct clksrc_clk clk_pclk_acp = {
298 .clk = { 278 .clk = {
299 .name = "pclk_acp", 279 .name = "pclk_acp",
300 .id = -1,
301 .parent = &clk_aclk_acp.clk, 280 .parent = &clk_aclk_acp.clk,
302 }, 281 },
303 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 282 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
318static struct clksrc_clk clk_aclk_200 = { 297static struct clksrc_clk clk_aclk_200 = {
319 .clk = { 298 .clk = {
320 .name = "aclk_200", 299 .name = "aclk_200",
321 .id = -1,
322 }, 300 },
323 .sources = &clkset_aclk, 301 .sources = &clkset_aclk,
324 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 302 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
328static struct clksrc_clk clk_aclk_100 = { 306static struct clksrc_clk clk_aclk_100 = {
329 .clk = { 307 .clk = {
330 .name = "aclk_100", 308 .name = "aclk_100",
331 .id = -1,
332 }, 309 },
333 .sources = &clkset_aclk, 310 .sources = &clkset_aclk,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 311 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
338static struct clksrc_clk clk_aclk_160 = { 315static struct clksrc_clk clk_aclk_160 = {
339 .clk = { 316 .clk = {
340 .name = "aclk_160", 317 .name = "aclk_160",
341 .id = -1,
342 }, 318 },
343 .sources = &clkset_aclk, 319 .sources = &clkset_aclk,
344 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 320 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
348static struct clksrc_clk clk_aclk_133 = { 324static struct clksrc_clk clk_aclk_133 = {
349 .clk = { 325 .clk = {
350 .name = "aclk_133", 326 .name = "aclk_133",
351 .id = -1,
352 }, 327 },
353 .sources = &clkset_aclk, 328 .sources = &clkset_aclk,
354 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
368static struct clksrc_clk clk_vpllsrc = { 343static struct clksrc_clk clk_vpllsrc = {
369 .clk = { 344 .clk = {
370 .name = "vpll_src", 345 .name = "vpll_src",
371 .id = -1,
372 .enable = exynos4_clksrc_mask_top_ctrl, 346 .enable = exynos4_clksrc_mask_top_ctrl,
373 .ctrlbit = (1 << 0), 347 .ctrlbit = (1 << 0),
374 }, 348 },
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
389static struct clksrc_clk clk_sclk_vpll = { 363static struct clksrc_clk clk_sclk_vpll = {
390 .clk = { 364 .clk = {
391 .name = "sclk_vpll", 365 .name = "sclk_vpll",
392 .id = -1,
393 }, 366 },
394 .sources = &clkset_sclk_vpll, 367 .sources = &clkset_sclk_vpll,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 368 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
398static struct clk init_clocks_off[] = { 371static struct clk init_clocks_off[] = {
399 { 372 {
400 .name = "timers", 373 .name = "timers",
401 .id = -1,
402 .parent = &clk_aclk_100.clk, 374 .parent = &clk_aclk_100.clk,
403 .enable = exynos4_clk_ip_peril_ctrl, 375 .enable = exynos4_clk_ip_peril_ctrl,
404 .ctrlbit = (1<<24), 376 .ctrlbit = (1<<24),
405 }, { 377 }, {
406 .name = "csis", 378 .name = "csis",
407 .id = 0, 379 .devname = "s5p-mipi-csis.0",
408 .enable = exynos4_clk_ip_cam_ctrl, 380 .enable = exynos4_clk_ip_cam_ctrl,
409 .ctrlbit = (1 << 4), 381 .ctrlbit = (1 << 4),
410 }, { 382 }, {
411 .name = "csis", 383 .name = "csis",
412 .id = 1, 384 .devname = "s5p-mipi-csis.1",
413 .enable = exynos4_clk_ip_cam_ctrl, 385 .enable = exynos4_clk_ip_cam_ctrl,
414 .ctrlbit = (1 << 5), 386 .ctrlbit = (1 << 5),
415 }, { 387 }, {
416 .name = "fimc", 388 .name = "fimc",
417 .id = 0, 389 .devname = "exynos4-fimc.0",
418 .enable = exynos4_clk_ip_cam_ctrl, 390 .enable = exynos4_clk_ip_cam_ctrl,
419 .ctrlbit = (1 << 0), 391 .ctrlbit = (1 << 0),
420 }, { 392 }, {
421 .name = "fimc", 393 .name = "fimc",
422 .id = 1, 394 .devname = "exynos4-fimc.1",
423 .enable = exynos4_clk_ip_cam_ctrl, 395 .enable = exynos4_clk_ip_cam_ctrl,
424 .ctrlbit = (1 << 1), 396 .ctrlbit = (1 << 1),
425 }, { 397 }, {
426 .name = "fimc", 398 .name = "fimc",
427 .id = 2, 399 .devname = "exynos4-fimc.2",
428 .enable = exynos4_clk_ip_cam_ctrl, 400 .enable = exynos4_clk_ip_cam_ctrl,
429 .ctrlbit = (1 << 2), 401 .ctrlbit = (1 << 2),
430 }, { 402 }, {
431 .name = "fimc", 403 .name = "fimc",
432 .id = 3, 404 .devname = "exynos4-fimc.3",
433 .enable = exynos4_clk_ip_cam_ctrl, 405 .enable = exynos4_clk_ip_cam_ctrl,
434 .ctrlbit = (1 << 3), 406 .ctrlbit = (1 << 3),
435 }, { 407 }, {
436 .name = "fimd", 408 .name = "fimd",
437 .id = 0, 409 .devname = "s5pv310-fb.0",
438 .enable = exynos4_clk_ip_lcd0_ctrl, 410 .enable = exynos4_clk_ip_lcd0_ctrl,
439 .ctrlbit = (1 << 0), 411 .ctrlbit = (1 << 0),
440 }, { 412 }, {
441 .name = "fimd", 413 .name = "fimd",
442 .id = 1, 414 .devname = "s5pv310-fb.1",
443 .enable = exynos4_clk_ip_lcd1_ctrl, 415 .enable = exynos4_clk_ip_lcd1_ctrl,
444 .ctrlbit = (1 << 0), 416 .ctrlbit = (1 << 0),
445 }, { 417 }, {
446 .name = "sataphy", 418 .name = "sataphy",
447 .id = -1,
448 .parent = &clk_aclk_133.clk, 419 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl, 420 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 3), 421 .ctrlbit = (1 << 3),
451 }, { 422 }, {
452 .name = "hsmmc", 423 .name = "hsmmc",
453 .id = 0, 424 .devname = "s3c-sdhci.0",
454 .parent = &clk_aclk_133.clk, 425 .parent = &clk_aclk_133.clk,
455 .enable = exynos4_clk_ip_fsys_ctrl, 426 .enable = exynos4_clk_ip_fsys_ctrl,
456 .ctrlbit = (1 << 5), 427 .ctrlbit = (1 << 5),
457 }, { 428 }, {
458 .name = "hsmmc", 429 .name = "hsmmc",
459 .id = 1, 430 .devname = "s3c-sdhci.1",
460 .parent = &clk_aclk_133.clk, 431 .parent = &clk_aclk_133.clk,
461 .enable = exynos4_clk_ip_fsys_ctrl, 432 .enable = exynos4_clk_ip_fsys_ctrl,
462 .ctrlbit = (1 << 6), 433 .ctrlbit = (1 << 6),
463 }, { 434 }, {
464 .name = "hsmmc", 435 .name = "hsmmc",
465 .id = 2, 436 .devname = "s3c-sdhci.2",
466 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
467 .enable = exynos4_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 7), 439 .ctrlbit = (1 << 7),
469 }, { 440 }, {
470 .name = "hsmmc", 441 .name = "hsmmc",
471 .id = 3, 442 .devname = "s3c-sdhci.3",
472 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
473 .enable = exynos4_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
474 .ctrlbit = (1 << 8), 445 .ctrlbit = (1 << 8),
475 }, { 446 }, {
476 .name = "hsmmc", 447 .name = "dwmmc",
477 .id = 4,
478 .parent = &clk_aclk_133.clk, 448 .parent = &clk_aclk_133.clk,
479 .enable = exynos4_clk_ip_fsys_ctrl, 449 .enable = exynos4_clk_ip_fsys_ctrl,
480 .ctrlbit = (1 << 9), 450 .ctrlbit = (1 << 9),
481 }, { 451 }, {
482 .name = "sata", 452 .name = "sata",
483 .id = -1,
484 .parent = &clk_aclk_133.clk, 453 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl, 454 .enable = exynos4_clk_ip_fsys_ctrl,
486 .ctrlbit = (1 << 10), 455 .ctrlbit = (1 << 10),
487 }, { 456 }, {
488 .name = "pdma", 457 .name = "pdma",
489 .id = 0, 458 .devname = "s3c-pl330.0",
490 .enable = exynos4_clk_ip_fsys_ctrl, 459 .enable = exynos4_clk_ip_fsys_ctrl,
491 .ctrlbit = (1 << 0), 460 .ctrlbit = (1 << 0),
492 }, { 461 }, {
493 .name = "pdma", 462 .name = "pdma",
494 .id = 1, 463 .devname = "s3c-pl330.1",
495 .enable = exynos4_clk_ip_fsys_ctrl, 464 .enable = exynos4_clk_ip_fsys_ctrl,
496 .ctrlbit = (1 << 1), 465 .ctrlbit = (1 << 1),
497 }, { 466 }, {
498 .name = "adc", 467 .name = "adc",
499 .id = -1,
500 .enable = exynos4_clk_ip_peril_ctrl, 468 .enable = exynos4_clk_ip_peril_ctrl,
501 .ctrlbit = (1 << 15), 469 .ctrlbit = (1 << 15),
502 }, { 470 }, {
503 .name = "keypad", 471 .name = "keypad",
504 .id = -1,
505 .enable = exynos4_clk_ip_perir_ctrl, 472 .enable = exynos4_clk_ip_perir_ctrl,
506 .ctrlbit = (1 << 16), 473 .ctrlbit = (1 << 16),
507 }, { 474 }, {
508 .name = "rtc", 475 .name = "rtc",
509 .id = -1,
510 .enable = exynos4_clk_ip_perir_ctrl, 476 .enable = exynos4_clk_ip_perir_ctrl,
511 .ctrlbit = (1 << 15), 477 .ctrlbit = (1 << 15),
512 }, { 478 }, {
513 .name = "watchdog", 479 .name = "watchdog",
514 .id = -1,
515 .parent = &clk_aclk_100.clk, 480 .parent = &clk_aclk_100.clk,
516 .enable = exynos4_clk_ip_perir_ctrl, 481 .enable = exynos4_clk_ip_perir_ctrl,
517 .ctrlbit = (1 << 14), 482 .ctrlbit = (1 << 14),
518 }, { 483 }, {
519 .name = "usbhost", 484 .name = "usbhost",
520 .id = -1,
521 .enable = exynos4_clk_ip_fsys_ctrl , 485 .enable = exynos4_clk_ip_fsys_ctrl ,
522 .ctrlbit = (1 << 12), 486 .ctrlbit = (1 << 12),
523 }, { 487 }, {
524 .name = "otg", 488 .name = "otg",
525 .id = -1,
526 .enable = exynos4_clk_ip_fsys_ctrl, 489 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 13), 490 .ctrlbit = (1 << 13),
528 }, { 491 }, {
529 .name = "spi", 492 .name = "spi",
530 .id = 0, 493 .devname = "s3c64xx-spi.0",
531 .enable = exynos4_clk_ip_peril_ctrl, 494 .enable = exynos4_clk_ip_peril_ctrl,
532 .ctrlbit = (1 << 16), 495 .ctrlbit = (1 << 16),
533 }, { 496 }, {
534 .name = "spi", 497 .name = "spi",
535 .id = 1, 498 .devname = "s3c64xx-spi.1",
536 .enable = exynos4_clk_ip_peril_ctrl, 499 .enable = exynos4_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 17), 500 .ctrlbit = (1 << 17),
538 }, { 501 }, {
539 .name = "spi", 502 .name = "spi",
540 .id = 2, 503 .devname = "s3c64xx-spi.2",
541 .enable = exynos4_clk_ip_peril_ctrl, 504 .enable = exynos4_clk_ip_peril_ctrl,
542 .ctrlbit = (1 << 18), 505 .ctrlbit = (1 << 18),
543 }, { 506 }, {
544 .name = "iis", 507 .name = "iis",
545 .id = 0, 508 .devname = "samsung-i2s.0",
546 .enable = exynos4_clk_ip_peril_ctrl, 509 .enable = exynos4_clk_ip_peril_ctrl,
547 .ctrlbit = (1 << 19), 510 .ctrlbit = (1 << 19),
548 }, { 511 }, {
549 .name = "iis", 512 .name = "iis",
550 .id = 1, 513 .devname = "samsung-i2s.1",
551 .enable = exynos4_clk_ip_peril_ctrl, 514 .enable = exynos4_clk_ip_peril_ctrl,
552 .ctrlbit = (1 << 20), 515 .ctrlbit = (1 << 20),
553 }, { 516 }, {
554 .name = "iis", 517 .name = "iis",
555 .id = 2, 518 .devname = "samsung-i2s.2",
556 .enable = exynos4_clk_ip_peril_ctrl, 519 .enable = exynos4_clk_ip_peril_ctrl,
557 .ctrlbit = (1 << 21), 520 .ctrlbit = (1 << 21),
558 }, { 521 }, {
@@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = {
562 .ctrlbit = (1 << 27), 525 .ctrlbit = (1 << 27),
563 }, { 526 }, {
564 .name = "fimg2d", 527 .name = "fimg2d",
565 .id = -1,
566 .enable = exynos4_clk_ip_image_ctrl, 528 .enable = exynos4_clk_ip_image_ctrl,
567 .ctrlbit = (1 << 0), 529 .ctrlbit = (1 << 0),
568 }, { 530 }, {
569 .name = "i2c", 531 .name = "i2c",
570 .id = 0, 532 .devname = "s3c2440-i2c.0",
571 .parent = &clk_aclk_100.clk, 533 .parent = &clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_peril_ctrl, 534 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 6), 535 .ctrlbit = (1 << 6),
574 }, { 536 }, {
575 .name = "i2c", 537 .name = "i2c",
576 .id = 1, 538 .devname = "s3c2440-i2c.1",
577 .parent = &clk_aclk_100.clk, 539 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_peril_ctrl, 540 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 7), 541 .ctrlbit = (1 << 7),
580 }, { 542 }, {
581 .name = "i2c", 543 .name = "i2c",
582 .id = 2, 544 .devname = "s3c2440-i2c.2",
583 .parent = &clk_aclk_100.clk, 545 .parent = &clk_aclk_100.clk,
584 .enable = exynos4_clk_ip_peril_ctrl, 546 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 8), 547 .ctrlbit = (1 << 8),
586 }, { 548 }, {
587 .name = "i2c", 549 .name = "i2c",
588 .id = 3, 550 .devname = "s3c2440-i2c.3",
589 .parent = &clk_aclk_100.clk, 551 .parent = &clk_aclk_100.clk,
590 .enable = exynos4_clk_ip_peril_ctrl, 552 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 9), 553 .ctrlbit = (1 << 9),
592 }, { 554 }, {
593 .name = "i2c", 555 .name = "i2c",
594 .id = 4, 556 .devname = "s3c2440-i2c.4",
595 .parent = &clk_aclk_100.clk, 557 .parent = &clk_aclk_100.clk,
596 .enable = exynos4_clk_ip_peril_ctrl, 558 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 10), 559 .ctrlbit = (1 << 10),
598 }, { 560 }, {
599 .name = "i2c", 561 .name = "i2c",
600 .id = 5, 562 .devname = "s3c2440-i2c.5",
601 .parent = &clk_aclk_100.clk, 563 .parent = &clk_aclk_100.clk,
602 .enable = exynos4_clk_ip_peril_ctrl, 564 .enable = exynos4_clk_ip_peril_ctrl,
603 .ctrlbit = (1 << 11), 565 .ctrlbit = (1 << 11),
604 }, { 566 }, {
605 .name = "i2c", 567 .name = "i2c",
606 .id = 6, 568 .devname = "s3c2440-i2c.6",
607 .parent = &clk_aclk_100.clk, 569 .parent = &clk_aclk_100.clk,
608 .enable = exynos4_clk_ip_peril_ctrl, 570 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 12), 571 .ctrlbit = (1 << 12),
610 }, { 572 }, {
611 .name = "i2c", 573 .name = "i2c",
612 .id = 7, 574 .devname = "s3c2440-i2c.7",
613 .parent = &clk_aclk_100.clk, 575 .parent = &clk_aclk_100.clk,
614 .enable = exynos4_clk_ip_peril_ctrl, 576 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 13), 577 .ctrlbit = (1 << 13),
616 }, { 578 }, {
617 .name = "SYSMMU_MDMA", 579 .name = "SYSMMU_MDMA",
618 .id = -1,
619 .enable = exynos4_clk_ip_image_ctrl, 580 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 5), 581 .ctrlbit = (1 << 5),
621 }, { 582 }, {
622 .name = "SYSMMU_FIMC0", 583 .name = "SYSMMU_FIMC0",
623 .id = -1,
624 .enable = exynos4_clk_ip_cam_ctrl, 584 .enable = exynos4_clk_ip_cam_ctrl,
625 .ctrlbit = (1 << 7), 585 .ctrlbit = (1 << 7),
626 }, { 586 }, {
627 .name = "SYSMMU_FIMC1", 587 .name = "SYSMMU_FIMC1",
628 .id = -1,
629 .enable = exynos4_clk_ip_cam_ctrl, 588 .enable = exynos4_clk_ip_cam_ctrl,
630 .ctrlbit = (1 << 8), 589 .ctrlbit = (1 << 8),
631 }, { 590 }, {
632 .name = "SYSMMU_FIMC2", 591 .name = "SYSMMU_FIMC2",
633 .id = -1,
634 .enable = exynos4_clk_ip_cam_ctrl, 592 .enable = exynos4_clk_ip_cam_ctrl,
635 .ctrlbit = (1 << 9), 593 .ctrlbit = (1 << 9),
636 }, { 594 }, {
637 .name = "SYSMMU_FIMC3", 595 .name = "SYSMMU_FIMC3",
638 .id = -1,
639 .enable = exynos4_clk_ip_cam_ctrl, 596 .enable = exynos4_clk_ip_cam_ctrl,
640 .ctrlbit = (1 << 10), 597 .ctrlbit = (1 << 10),
641 }, { 598 }, {
642 .name = "SYSMMU_JPEG", 599 .name = "SYSMMU_JPEG",
643 .id = -1,
644 .enable = exynos4_clk_ip_cam_ctrl, 600 .enable = exynos4_clk_ip_cam_ctrl,
645 .ctrlbit = (1 << 11), 601 .ctrlbit = (1 << 11),
646 }, { 602 }, {
647 .name = "SYSMMU_FIMD0", 603 .name = "SYSMMU_FIMD0",
648 .id = -1,
649 .enable = exynos4_clk_ip_lcd0_ctrl, 604 .enable = exynos4_clk_ip_lcd0_ctrl,
650 .ctrlbit = (1 << 4), 605 .ctrlbit = (1 << 4),
651 }, { 606 }, {
652 .name = "SYSMMU_FIMD1", 607 .name = "SYSMMU_FIMD1",
653 .id = -1,
654 .enable = exynos4_clk_ip_lcd1_ctrl, 608 .enable = exynos4_clk_ip_lcd1_ctrl,
655 .ctrlbit = (1 << 4), 609 .ctrlbit = (1 << 4),
656 }, { 610 }, {
657 .name = "SYSMMU_PCIe", 611 .name = "SYSMMU_PCIe",
658 .id = -1,
659 .enable = exynos4_clk_ip_fsys_ctrl, 612 .enable = exynos4_clk_ip_fsys_ctrl,
660 .ctrlbit = (1 << 18), 613 .ctrlbit = (1 << 18),
661 }, { 614 }, {
662 .name = "SYSMMU_G2D", 615 .name = "SYSMMU_G2D",
663 .id = -1,
664 .enable = exynos4_clk_ip_image_ctrl, 616 .enable = exynos4_clk_ip_image_ctrl,
665 .ctrlbit = (1 << 3), 617 .ctrlbit = (1 << 3),
666 }, { 618 }, {
667 .name = "SYSMMU_ROTATOR", 619 .name = "SYSMMU_ROTATOR",
668 .id = -1,
669 .enable = exynos4_clk_ip_image_ctrl, 620 .enable = exynos4_clk_ip_image_ctrl,
670 .ctrlbit = (1 << 4), 621 .ctrlbit = (1 << 4),
671 }, { 622 }, {
672 .name = "SYSMMU_TV", 623 .name = "SYSMMU_TV",
673 .id = -1,
674 .enable = exynos4_clk_ip_tv_ctrl, 624 .enable = exynos4_clk_ip_tv_ctrl,
675 .ctrlbit = (1 << 4), 625 .ctrlbit = (1 << 4),
676 }, { 626 }, {
677 .name = "SYSMMU_MFC_L", 627 .name = "SYSMMU_MFC_L",
678 .id = -1,
679 .enable = exynos4_clk_ip_mfc_ctrl, 628 .enable = exynos4_clk_ip_mfc_ctrl,
680 .ctrlbit = (1 << 1), 629 .ctrlbit = (1 << 1),
681 }, { 630 }, {
682 .name = "SYSMMU_MFC_R", 631 .name = "SYSMMU_MFC_R",
683 .id = -1,
684 .enable = exynos4_clk_ip_mfc_ctrl, 632 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 2), 633 .ctrlbit = (1 << 2),
686 } 634 }
@@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = {
689static struct clk init_clocks[] = { 637static struct clk init_clocks[] = {
690 { 638 {
691 .name = "uart", 639 .name = "uart",
692 .id = 0, 640 .devname = "s5pv210-uart.0",
693 .enable = exynos4_clk_ip_peril_ctrl, 641 .enable = exynos4_clk_ip_peril_ctrl,
694 .ctrlbit = (1 << 0), 642 .ctrlbit = (1 << 0),
695 }, { 643 }, {
696 .name = "uart", 644 .name = "uart",
697 .id = 1, 645 .devname = "s5pv210-uart.1",
698 .enable = exynos4_clk_ip_peril_ctrl, 646 .enable = exynos4_clk_ip_peril_ctrl,
699 .ctrlbit = (1 << 1), 647 .ctrlbit = (1 << 1),
700 }, { 648 }, {
701 .name = "uart", 649 .name = "uart",
702 .id = 2, 650 .devname = "s5pv210-uart.2",
703 .enable = exynos4_clk_ip_peril_ctrl, 651 .enable = exynos4_clk_ip_peril_ctrl,
704 .ctrlbit = (1 << 2), 652 .ctrlbit = (1 << 2),
705 }, { 653 }, {
706 .name = "uart", 654 .name = "uart",
707 .id = 3, 655 .devname = "s5pv210-uart.3",
708 .enable = exynos4_clk_ip_peril_ctrl, 656 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 3), 657 .ctrlbit = (1 << 3),
710 }, { 658 }, {
711 .name = "uart", 659 .name = "uart",
712 .id = 4, 660 .devname = "s5pv210-uart.4",
713 .enable = exynos4_clk_ip_peril_ctrl, 661 .enable = exynos4_clk_ip_peril_ctrl,
714 .ctrlbit = (1 << 4), 662 .ctrlbit = (1 << 4),
715 }, { 663 }, {
716 .name = "uart", 664 .name = "uart",
717 .id = 5, 665 .devname = "s5pv210-uart.5",
718 .enable = exynos4_clk_ip_peril_ctrl, 666 .enable = exynos4_clk_ip_peril_ctrl,
719 .ctrlbit = (1 << 5), 667 .ctrlbit = (1 << 5),
720 } 668 }
@@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
750static struct clksrc_clk clk_mout_g2d0 = { 698static struct clksrc_clk clk_mout_g2d0 = {
751 .clk = { 699 .clk = {
752 .name = "mout_g2d0", 700 .name = "mout_g2d0",
753 .id = -1,
754 }, 701 },
755 .sources = &clkset_mout_g2d0, 702 .sources = &clkset_mout_g2d0,
756 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 703 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
769static struct clksrc_clk clk_mout_g2d1 = { 716static struct clksrc_clk clk_mout_g2d1 = {
770 .clk = { 717 .clk = {
771 .name = "mout_g2d1", 718 .name = "mout_g2d1",
772 .id = -1,
773 }, 719 },
774 .sources = &clkset_mout_g2d1, 720 .sources = &clkset_mout_g2d1,
775 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 721 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = {
788static struct clksrc_clk clk_dout_mmc0 = { 734static struct clksrc_clk clk_dout_mmc0 = {
789 .clk = { 735 .clk = {
790 .name = "dout_mmc0", 736 .name = "dout_mmc0",
791 .id = -1,
792 }, 737 },
793 .sources = &clkset_group, 738 .sources = &clkset_group,
794 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, 739 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
798static struct clksrc_clk clk_dout_mmc1 = { 743static struct clksrc_clk clk_dout_mmc1 = {
799 .clk = { 744 .clk = {
800 .name = "dout_mmc1", 745 .name = "dout_mmc1",
801 .id = -1,
802 }, 746 },
803 .sources = &clkset_group, 747 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, 748 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
808static struct clksrc_clk clk_dout_mmc2 = { 752static struct clksrc_clk clk_dout_mmc2 = {
809 .clk = { 753 .clk = {
810 .name = "dout_mmc2", 754 .name = "dout_mmc2",
811 .id = -1,
812 }, 755 },
813 .sources = &clkset_group, 756 .sources = &clkset_group,
814 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, 757 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
818static struct clksrc_clk clk_dout_mmc3 = { 761static struct clksrc_clk clk_dout_mmc3 = {
819 .clk = { 762 .clk = {
820 .name = "dout_mmc3", 763 .name = "dout_mmc3",
821 .id = -1,
822 }, 764 },
823 .sources = &clkset_group, 765 .sources = &clkset_group,
824 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, 766 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
828static struct clksrc_clk clk_dout_mmc4 = { 770static struct clksrc_clk clk_dout_mmc4 = {
829 .clk = { 771 .clk = {
830 .name = "dout_mmc4", 772 .name = "dout_mmc4",
831 .id = -1,
832 }, 773 },
833 .sources = &clkset_group, 774 .sources = &clkset_group,
834 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, 775 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
839 { 780 {
840 .clk = { 781 .clk = {
841 .name = "uclk1", 782 .name = "uclk1",
842 .id = 0, 783 .devname = "s5pv210-uart.0",
843 .enable = exynos4_clksrc_mask_peril0_ctrl, 784 .enable = exynos4_clksrc_mask_peril0_ctrl,
844 .ctrlbit = (1 << 0), 785 .ctrlbit = (1 << 0),
845 }, 786 },
@@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 790 }, {
850 .clk = { 791 .clk = {
851 .name = "uclk1", 792 .name = "uclk1",
852 .id = 1, 793 .devname = "s5pv210-uart.1",
853 .enable = exynos4_clksrc_mask_peril0_ctrl, 794 .enable = exynos4_clksrc_mask_peril0_ctrl,
854 .ctrlbit = (1 << 4), 795 .ctrlbit = (1 << 4),
855 }, 796 },
@@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
859 }, { 800 }, {
860 .clk = { 801 .clk = {
861 .name = "uclk1", 802 .name = "uclk1",
862 .id = 2, 803 .devname = "s5pv210-uart.2",
863 .enable = exynos4_clksrc_mask_peril0_ctrl, 804 .enable = exynos4_clksrc_mask_peril0_ctrl,
864 .ctrlbit = (1 << 8), 805 .ctrlbit = (1 << 8),
865 }, 806 },
@@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
869 }, { 810 }, {
870 .clk = { 811 .clk = {
871 .name = "uclk1", 812 .name = "uclk1",
872 .id = 3, 813 .devname = "s5pv210-uart.3",
873 .enable = exynos4_clksrc_mask_peril0_ctrl, 814 .enable = exynos4_clksrc_mask_peril0_ctrl,
874 .ctrlbit = (1 << 12), 815 .ctrlbit = (1 << 12),
875 }, 816 },
@@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = {
879 }, { 820 }, {
880 .clk = { 821 .clk = {
881 .name = "sclk_pwm", 822 .name = "sclk_pwm",
882 .id = -1,
883 .enable = exynos4_clksrc_mask_peril0_ctrl, 823 .enable = exynos4_clksrc_mask_peril0_ctrl,
884 .ctrlbit = (1 << 24), 824 .ctrlbit = (1 << 24),
885 }, 825 },
@@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = {
889 }, { 829 }, {
890 .clk = { 830 .clk = {
891 .name = "sclk_csis", 831 .name = "sclk_csis",
892 .id = 0, 832 .devname = "s5p-mipi-csis.0",
893 .enable = exynos4_clksrc_mask_cam_ctrl, 833 .enable = exynos4_clksrc_mask_cam_ctrl,
894 .ctrlbit = (1 << 24), 834 .ctrlbit = (1 << 24),
895 }, 835 },
@@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
899 }, { 839 }, {
900 .clk = { 840 .clk = {
901 .name = "sclk_csis", 841 .name = "sclk_csis",
902 .id = 1, 842 .devname = "s5p-mipi-csis.1",
903 .enable = exynos4_clksrc_mask_cam_ctrl, 843 .enable = exynos4_clksrc_mask_cam_ctrl,
904 .ctrlbit = (1 << 28), 844 .ctrlbit = (1 << 28),
905 }, 845 },
@@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
909 }, { 849 }, {
910 .clk = { 850 .clk = {
911 .name = "sclk_cam", 851 .name = "sclk_cam",
912 .id = 0, 852 .devname = "exynos4-fimc.0",
913 .enable = exynos4_clksrc_mask_cam_ctrl, 853 .enable = exynos4_clksrc_mask_cam_ctrl,
914 .ctrlbit = (1 << 16), 854 .ctrlbit = (1 << 16),
915 }, 855 },
@@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
919 }, { 859 }, {
920 .clk = { 860 .clk = {
921 .name = "sclk_cam", 861 .name = "sclk_cam",
922 .id = 1, 862 .devname = "exynos4-fimc.1",
923 .enable = exynos4_clksrc_mask_cam_ctrl, 863 .enable = exynos4_clksrc_mask_cam_ctrl,
924 .ctrlbit = (1 << 20), 864 .ctrlbit = (1 << 20),
925 }, 865 },
@@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
929 }, { 869 }, {
930 .clk = { 870 .clk = {
931 .name = "sclk_fimc", 871 .name = "sclk_fimc",
932 .id = 0, 872 .devname = "exynos4-fimc.0",
933 .enable = exynos4_clksrc_mask_cam_ctrl, 873 .enable = exynos4_clksrc_mask_cam_ctrl,
934 .ctrlbit = (1 << 0), 874 .ctrlbit = (1 << 0),
935 }, 875 },
@@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = {
939 }, { 879 }, {
940 .clk = { 880 .clk = {
941 .name = "sclk_fimc", 881 .name = "sclk_fimc",
942 .id = 1, 882 .devname = "exynos4-fimc.1",
943 .enable = exynos4_clksrc_mask_cam_ctrl, 883 .enable = exynos4_clksrc_mask_cam_ctrl,
944 .ctrlbit = (1 << 4), 884 .ctrlbit = (1 << 4),
945 }, 885 },
@@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = {
949 }, { 889 }, {
950 .clk = { 890 .clk = {
951 .name = "sclk_fimc", 891 .name = "sclk_fimc",
952 .id = 2, 892 .devname = "exynos4-fimc.2",
953 .enable = exynos4_clksrc_mask_cam_ctrl, 893 .enable = exynos4_clksrc_mask_cam_ctrl,
954 .ctrlbit = (1 << 8), 894 .ctrlbit = (1 << 8),
955 }, 895 },
@@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = {
959 }, { 899 }, {
960 .clk = { 900 .clk = {
961 .name = "sclk_fimc", 901 .name = "sclk_fimc",
962 .id = 3, 902 .devname = "exynos4-fimc.3",
963 .enable = exynos4_clksrc_mask_cam_ctrl, 903 .enable = exynos4_clksrc_mask_cam_ctrl,
964 .ctrlbit = (1 << 12), 904 .ctrlbit = (1 << 12),
965 }, 905 },
@@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = {
969 }, { 909 }, {
970 .clk = { 910 .clk = {
971 .name = "sclk_fimd", 911 .name = "sclk_fimd",
972 .id = 0, 912 .devname = "s5pv310-fb.0",
973 .enable = exynos4_clksrc_mask_lcd0_ctrl, 913 .enable = exynos4_clksrc_mask_lcd0_ctrl,
974 .ctrlbit = (1 << 0), 914 .ctrlbit = (1 << 0),
975 }, 915 },
@@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = {
979 }, { 919 }, {
980 .clk = { 920 .clk = {
981 .name = "sclk_fimd", 921 .name = "sclk_fimd",
982 .id = 1, 922 .devname = "s5pv310-fb.1",
983 .enable = exynos4_clksrc_mask_lcd1_ctrl, 923 .enable = exynos4_clksrc_mask_lcd1_ctrl,
984 .ctrlbit = (1 << 0), 924 .ctrlbit = (1 << 0),
985 }, 925 },
@@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = {
989 }, { 929 }, {
990 .clk = { 930 .clk = {
991 .name = "sclk_sata", 931 .name = "sclk_sata",
992 .id = -1,
993 .enable = exynos4_clksrc_mask_fsys_ctrl, 932 .enable = exynos4_clksrc_mask_fsys_ctrl,
994 .ctrlbit = (1 << 24), 933 .ctrlbit = (1 << 24),
995 }, 934 },
@@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = {
999 }, { 938 }, {
1000 .clk = { 939 .clk = {
1001 .name = "sclk_spi", 940 .name = "sclk_spi",
1002 .id = 0, 941 .devname = "s3c64xx-spi.0",
1003 .enable = exynos4_clksrc_mask_peril1_ctrl, 942 .enable = exynos4_clksrc_mask_peril1_ctrl,
1004 .ctrlbit = (1 << 16), 943 .ctrlbit = (1 << 16),
1005 }, 944 },
@@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = {
1009 }, { 948 }, {
1010 .clk = { 949 .clk = {
1011 .name = "sclk_spi", 950 .name = "sclk_spi",
1012 .id = 1, 951 .devname = "s3c64xx-spi.1",
1013 .enable = exynos4_clksrc_mask_peril1_ctrl, 952 .enable = exynos4_clksrc_mask_peril1_ctrl,
1014 .ctrlbit = (1 << 20), 953 .ctrlbit = (1 << 20),
1015 }, 954 },
@@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = {
1019 }, { 958 }, {
1020 .clk = { 959 .clk = {
1021 .name = "sclk_spi", 960 .name = "sclk_spi",
1022 .id = 2, 961 .devname = "s3c64xx-spi.2",
1023 .enable = exynos4_clksrc_mask_peril1_ctrl, 962 .enable = exynos4_clksrc_mask_peril1_ctrl,
1024 .ctrlbit = (1 << 24), 963 .ctrlbit = (1 << 24),
1025 }, 964 },
@@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
1029 }, { 968 }, {
1030 .clk = { 969 .clk = {
1031 .name = "sclk_fimg2d", 970 .name = "sclk_fimg2d",
1032 .id = -1,
1033 }, 971 },
1034 .sources = &clkset_mout_g2d, 972 .sources = &clkset_mout_g2d,
1035 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 973 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = {
1037 }, { 975 }, {
1038 .clk = { 976 .clk = {
1039 .name = "sclk_mmc", 977 .name = "sclk_mmc",
1040 .id = 0, 978 .devname = "s3c-sdhci.0",
1041 .parent = &clk_dout_mmc0.clk, 979 .parent = &clk_dout_mmc0.clk,
1042 .enable = exynos4_clksrc_mask_fsys_ctrl, 980 .enable = exynos4_clksrc_mask_fsys_ctrl,
1043 .ctrlbit = (1 << 0), 981 .ctrlbit = (1 << 0),
@@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = {
1046 }, { 984 }, {
1047 .clk = { 985 .clk = {
1048 .name = "sclk_mmc", 986 .name = "sclk_mmc",
1049 .id = 1, 987 .devname = "s3c-sdhci.1",
1050 .parent = &clk_dout_mmc1.clk, 988 .parent = &clk_dout_mmc1.clk,
1051 .enable = exynos4_clksrc_mask_fsys_ctrl, 989 .enable = exynos4_clksrc_mask_fsys_ctrl,
1052 .ctrlbit = (1 << 4), 990 .ctrlbit = (1 << 4),
@@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = {
1055 }, { 993 }, {
1056 .clk = { 994 .clk = {
1057 .name = "sclk_mmc", 995 .name = "sclk_mmc",
1058 .id = 2, 996 .devname = "s3c-sdhci.2",
1059 .parent = &clk_dout_mmc2.clk, 997 .parent = &clk_dout_mmc2.clk,
1060 .enable = exynos4_clksrc_mask_fsys_ctrl, 998 .enable = exynos4_clksrc_mask_fsys_ctrl,
1061 .ctrlbit = (1 << 8), 999 .ctrlbit = (1 << 8),
@@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = {
1064 }, { 1002 }, {
1065 .clk = { 1003 .clk = {
1066 .name = "sclk_mmc", 1004 .name = "sclk_mmc",
1067 .id = 3, 1005 .devname = "s3c-sdhci.3",
1068 .parent = &clk_dout_mmc3.clk, 1006 .parent = &clk_dout_mmc3.clk,
1069 .enable = exynos4_clksrc_mask_fsys_ctrl, 1007 .enable = exynos4_clksrc_mask_fsys_ctrl,
1070 .ctrlbit = (1 << 12), 1008 .ctrlbit = (1 << 12),
@@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1010 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1073 }, { 1011 }, {
1074 .clk = { 1012 .clk = {
1075 .name = "sclk_mmc", 1013 .name = "sclk_dwmmc",
1076 .id = 4,
1077 .parent = &clk_dout_mmc4.clk, 1014 .parent = &clk_dout_mmc4.clk,
1078 .enable = exynos4_clksrc_mask_fsys_ctrl, 1015 .enable = exynos4_clksrc_mask_fsys_ctrl,
1079 .ctrlbit = (1 << 16), 1016 .ctrlbit = (1 << 16),
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 05:13:49 -0500