ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos

The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
made for plaforms based on EXYNOS4 SoCs. But since upcoming
Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
codes in current mach-exynos4, one mach-exynos directory will
be used for them.

This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
avoid changing in driver side.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 136 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
new file mode 100644
index 000000000000..39aca045f660
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-usb-phy.h>
+#include <plat/cpu.h>
+#include <plat/usb-phy.h>
+
+static int exynos4_usb_phy1_init(struct platform_device *pdev)
+{
+        struct clk *otg_clk;
+        struct clk *xusbxti_clk;
+        u32 phyclk;
+        u32 rstcon;
+        int err;
+
+        otg_clk = clk_get(&pdev->dev, "otg");
+        if (IS_ERR(otg_clk)) {
+                dev_err(&pdev->dev, "Failed to get otg clock\n");
+                return PTR_ERR(otg_clk);
+        }
+
+        err = clk_enable(otg_clk);
+        if (err) {
+                clk_put(otg_clk);
+                return err;
+        }
+
+        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
+                        S5P_USBHOST_PHY_CONTROL);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
+
+        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
+                switch (clk_get_rate(xusbxti_clk)) {
+                case 12 * MHZ:
+                        phyclk |= CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti_clk);
+        }
+
+        writel(phyclk, EXYNOS4_PHYCLK);
+
+        /* floating prevention logic: disable */
+        writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
+
+        /* set to normal HSIC 0 and 1 of PHY1 */
+        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
+                        EXYNOS4_PHYPWR);
+
+        /* set to normal standard USB of PHY1 */
+        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
+
+        /* reset all ports of both PHY and Link */
+        rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
+                PHY1_SWRST_MASK;
+        writel(rstcon, EXYNOS4_RSTCON);
+        udelay(10);
+
+        rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
+        writel(rstcon, EXYNOS4_RSTCON);
+        udelay(80);
+
+        clk_disable(otg_clk);
+        clk_put(otg_clk);
+
+        return 0;
+}
+
+static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+{
+        struct clk *otg_clk;
+        int err;
+
+        otg_clk = clk_get(&pdev->dev, "otg");
+        if (IS_ERR(otg_clk)) {
+                dev_err(&pdev->dev, "Failed to get otg clock\n");
+                return PTR_ERR(otg_clk);
+        }
+
+        err = clk_enable(otg_clk);
+        if (err) {
+                clk_put(otg_clk);
+                return err;
+        }
+
+        writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
+                        EXYNOS4_PHYPWR);
+
+        writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
+                        S5P_USBHOST_PHY_CONTROL);
+
+        clk_disable(otg_clk);
+        clk_put(otg_clk);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_HOST)
+                return exynos4_usb_phy1_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_HOST)
+                return exynos4_usb_phy1_exit(pdev);
+
+        return -EINVAL;
+}