diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2013-12-18 14:19:59 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-12-18 15:21:17 -0500 |
commit | 9c9239afe31f67d137ba6c45b244b509c2090567 (patch) | |
tree | e832d8ff75bf0f74f0a073f84c37158943b05463 /arch/arm/mach-exynos/pm.c | |
parent | 7d8f159188410557630a7270efe3e14a1a305c2e (diff) |
ARM: EXYNOS: local definitions for pm.c into mach-exynos dir
Some of definitions in the regs-clock.h are used only for pm.c,
so this moves them into the file.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
-rw-r--r-- | arch/arm/mach-exynos/pm.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 11c37c4f04fb..e00025bbbe89 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -29,12 +29,36 @@ | |||
29 | #include <plat/pll.h> | 29 | #include <plat/pll.h> |
30 | #include <plat/regs-srom.h> | 30 | #include <plat/regs-srom.h> |
31 | 31 | ||
32 | #include <mach/regs-clock.h> | 32 | #include <mach/map.h> |
33 | #include <mach/pm-core.h> | 33 | #include <mach/pm-core.h> |
34 | 34 | ||
35 | #include "common.h" | 35 | #include "common.h" |
36 | #include "regs-pmu.h" | 36 | #include "regs-pmu.h" |
37 | 37 | ||
38 | #define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) | ||
39 | #define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) | ||
40 | |||
41 | #define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) | ||
42 | #define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) | ||
43 | #define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) | ||
44 | #define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) | ||
45 | |||
46 | #define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) | ||
47 | #define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) | ||
48 | #define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) | ||
49 | #define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) | ||
50 | #define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) | ||
51 | #define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) | ||
52 | #define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) | ||
53 | #define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) | ||
54 | |||
55 | #define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) | ||
56 | |||
57 | #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) | ||
58 | #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) | ||
59 | |||
60 | #define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) | ||
61 | |||
38 | static const struct sleep_save exynos4_set_clksrc[] = { | 62 | static const struct sleep_save exynos4_set_clksrc[] = { |
39 | { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, | 63 | { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, |
40 | { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, | 64 | { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, |