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author | Olof Johansson <olof@lixom.net> | 2012-03-10 12:51:26 -0500 |
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committer | Olof Johansson <olof@lixom.net> | 2012-03-10 12:51:26 -0500 |
commit | f7c8faedf98aa5ec372e0191078ac7fe1e7fb067 (patch) | |
tree | 14e69d0e6022e23850611abdc1b48770b921c193 /arch/arm/mach-exynos/pm.c | |
parent | acf346084bca289a00020a5c29c23673b801b380 (diff) | |
parent | 4d2e4d7f2c2b1a4382286821a59fa2f4012cb748 (diff) |
Merge branch 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: fix cycle count for periodic mode of clock event timers
ARM: EXYNOS: add support JPEG
ARM: EXYNOS: Add DMC1, allow PPMU access for DMC
ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition
ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata()
ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
ARM: S5PV210: Add usb otg phy control
ARM: S3C64XX: Add usb otg phy control
ARM: EXYNOS: Enable l2 configuration through device tree
ARM: EXYNOS: remove useless code to save/restore L2
ARM: EXYNOS: save L2 settings during bootup
ARM: S5P: add L2 early resume code
ARM: EXYNOS: Add support AFTR mode on EXYNOS4210
ARM: SAMSUNG: use spin_lock_irqsave() in clk_{enable,disable}
ARM: S3C64XX: Define some additional always off clocks
ARM: S3C64XX: Reduce residency requirement for cpuidle WFI mode
ARM: SAMSUNG: Add a callback 'notify_after' for PWM backlight control
ARM: SAMSUNG: add G2D to plat-s5p and mach-exynos
ARM: S3C64XX: Gate some more clocks by default
ARM: S3C64XX: Add basic cpuidle driver
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
-rw-r--r-- | arch/arm/mach-exynos/pm.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e19013051772..481682745e7d 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { | |||
155 | SAVE_ITEM(S5P_SROM_BC3), | 155 | SAVE_ITEM(S5P_SROM_BC3), |
156 | }; | 156 | }; |
157 | 157 | ||
158 | static struct sleep_save exynos4_l2cc_save[] = { | ||
159 | SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), | ||
160 | SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), | ||
161 | SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), | ||
162 | SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), | ||
163 | SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), | ||
164 | }; | ||
165 | 158 | ||
166 | /* For Cortex-A9 Diagnostic and Power control register */ | 159 | /* For Cortex-A9 Diagnostic and Power control register */ |
167 | static unsigned int save_arm_register[2]; | 160 | static unsigned int save_arm_register[2]; |
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) | |||
182 | u32 tmp; | 175 | u32 tmp; |
183 | 176 | ||
184 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); | 177 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); |
185 | s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | ||
186 | s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); | 178 | s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); |
187 | s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); | 179 | s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); |
188 | 180 | ||
@@ -388,13 +380,6 @@ static void exynos4_pm_resume(void) | |||
388 | scu_enable(S5P_VA_SCU); | 380 | scu_enable(S5P_VA_SCU); |
389 | #endif | 381 | #endif |
390 | 382 | ||
391 | #ifdef CONFIG_CACHE_L2X0 | ||
392 | s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | ||
393 | outer_inv_all(); | ||
394 | /* enable L2X0*/ | ||
395 | writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); | ||
396 | #endif | ||
397 | |||
398 | early_wakeup: | 383 | early_wakeup: |
399 | return; | 384 | return; |
400 | } | 385 | } |