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authorKukjin Kim <kgene.kim@samsung.com>2012-02-09 21:57:53 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-14 05:13:05 -0400
commit171c067c1a3f903fca78f2610794441a7d1e64f3 (patch)
tree62ea5441364f1c2288f5855dbbc6828e9f7808cb /arch/arm/mach-exynos/include
parentb67545fd9b5335c38c028e7984a1bef9e789c8dc (diff)
ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
Actually, the base address of uart is different between EXYNOS4 and EXYNOS5 and this patch enables to support uart for EXYNOS4 and EXYNOS5 SoCs at runtime. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include')
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S9
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h17
4 files changed, 42 insertions, 16 deletions
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a6..6c857ff0b5d8 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
21 */ 21 */
22 22
23 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART 24 mov \rp, #0x10000000
25 ldr \rv, = S3C_VA_UART 25 ldr \rp, [\rp, #0x0]
26 and \rp, \rp, #0xf00000
27 teq \rp, #0x500000 @@ EXYNOS5
28 ldreq \rp, =EXYNOS5_PA_UART
29 movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
30 ldr \rv, =S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0 31#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 32 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) 33 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1d401c957835..f78070ee79f0 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -173,4 +173,16 @@
173/* Set the default NR_IRQS */ 173/* Set the default NR_IRQS */
174#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) 174#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
175 175
176#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
177#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
178#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
179#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
180#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
181
182#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
183#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
184#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
185#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
186#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
187
176#endif /* __ASM_ARCH_IRQS_H */ 188#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 2ad4e9cfe498..ea513c626b12 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -153,7 +153,6 @@
153#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 153#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
154#define S3C_PA_RTC EXYNOS4_PA_RTC 154#define S3C_PA_RTC EXYNOS4_PA_RTC
155#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 155#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
156#define S3C_PA_UART EXYNOS4_PA_UART
157#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 156#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
158#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 157#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
159#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 158#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
@@ -182,15 +181,18 @@
182 181
183/* Compatibility UART */ 182/* Compatibility UART */
184 183
185#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 184#define EXYNOS4_PA_UART0 0x13800000
185#define EXYNOS4_PA_UART1 0x13810000
186#define EXYNOS4_PA_UART2 0x13820000
187#define EXYNOS4_PA_UART3 0x13830000
188#define EXYNOS4_SZ_UART SZ_256
186 189
187#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) 190#define EXYNOS5_PA_UART0 0x12C00000
188#define S5P_PA_UART0 S5P_PA_UART(0) 191#define EXYNOS5_PA_UART1 0x12C10000
189#define S5P_PA_UART1 S5P_PA_UART(1) 192#define EXYNOS5_PA_UART2 0x12C20000
190#define S5P_PA_UART2 S5P_PA_UART(2) 193#define EXYNOS5_PA_UART3 0x12C30000
191#define S5P_PA_UART3 S5P_PA_UART(3) 194#define EXYNOS5_SZ_UART SZ_256
192#define S5P_PA_UART4 S5P_PA_UART(4)
193 195
194#define S5P_SZ_UART SZ_256 196#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
195 197
196#endif /* __ASM_ARCH_MAP_H */ 198#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9acb..493f4f365ddf 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - uncompress code 5 * EXYNOS - uncompress code
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 12#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__ 13#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15 14
15#include <asm/mach-types.h>
16
16#include <mach/map.h> 17#include <mach/map.h>
18
19volatile u8 *uart_base;
20
17#include <plat/uncompress.h> 21#include <plat/uncompress.h>
18 22
19static void arch_detect_cpu(void) 23static void arch_detect_cpu(void)
20{ 24{
21 /* we do not need to do any cpu detection here at the moment. */ 25 if (machine_is_smdk5250())
26 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
27 else
28 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
22 29
23 /* 30 /*
24 * For preventing FIFO overrun or infinite loop of UART console, 31 * For preventing FIFO overrun or infinite loop of UART console,