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authorKukjin Kim <kgene.kim@samsung.com>2012-11-15 01:48:56 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-11-21 23:09:18 -0500
commit2edb36c4ea09fe5077e2d19e60fd353ab1fc6eee (patch)
tree2d2557688f94d7fd6f734a7a97fe33a1cde75ff6 /arch/arm/mach-exynos/common.c
parent77b67063bb6bce6d475e910d3b886a606d0d91f7 (diff)
ARM: EXYNOS: add support for EXYNOS5440 SoC
This patch adds support for EXYNOS5440 SoC which is including ARM Cortex-A15 Quad cores. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r--arch/arm/mach-exynos/common.c68
1 files changed, 62 insertions, 6 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1947be8e5f5b..94f1dedc0617 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -58,9 +58,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
58static const char name_exynos4212[] = "EXYNOS4212"; 58static const char name_exynos4212[] = "EXYNOS4212";
59static const char name_exynos4412[] = "EXYNOS4412"; 59static const char name_exynos4412[] = "EXYNOS4412";
60static const char name_exynos5250[] = "EXYNOS5250"; 60static const char name_exynos5250[] = "EXYNOS5250";
61static const char name_exynos5440[] = "EXYNOS5440";
61 62
62static void exynos4_map_io(void); 63static void exynos4_map_io(void);
63static void exynos5_map_io(void); 64static void exynos5_map_io(void);
65static void exynos5440_map_io(void);
64static void exynos4_init_clocks(int xtal); 66static void exynos4_init_clocks(int xtal);
65static void exynos5_init_clocks(int xtal); 67static void exynos5_init_clocks(int xtal);
66static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no); 68static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
@@ -99,6 +101,12 @@ static struct cpu_table cpu_ids[] __initdata = {
99 .init_uarts = exynos_init_uarts, 101 .init_uarts = exynos_init_uarts,
100 .init = exynos_init, 102 .init = exynos_init,
101 .name = name_exynos5250, 103 .name = name_exynos5250,
104 }, {
105 .idcode = EXYNOS5440_SOC_ID,
106 .idmask = EXYNOS5_SOC_MASK,
107 .map_io = exynos5440_map_io,
108 .init = exynos_init,
109 .name = name_exynos5440,
102 }, 110 },
103}; 111};
104 112
@@ -113,6 +121,15 @@ static struct map_desc exynos_iodesc[] __initdata = {
113 }, 121 },
114}; 122};
115 123
124static struct map_desc exynos5440_iodesc[] __initdata = {
125 {
126 .virtual = (unsigned long)S5P_VA_CHIPID,
127 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
128 .length = SZ_4K,
129 .type = MT_DEVICE,
130 },
131};
132
116static struct map_desc exynos4_iodesc[] __initdata = { 133static struct map_desc exynos4_iodesc[] __initdata = {
117 { 134 {
118 .virtual = (unsigned long)S3C_VA_SYS, 135 .virtual = (unsigned long)S3C_VA_SYS,
@@ -279,6 +296,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
279 }, 296 },
280}; 297};
281 298
299static struct map_desc exynos5440_iodesc0[] __initdata = {
300 {
301 .virtual = (unsigned long)S3C_VA_UART,
302 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
303 .length = SZ_512K,
304 .type = MT_DEVICE,
305 },
306};
307
282void exynos4_restart(char mode, const char *cmd) 308void exynos4_restart(char mode, const char *cmd)
283{ 309{
284 __raw_writel(0x1, S5P_SWRESET); 310 __raw_writel(0x1, S5P_SWRESET);
@@ -286,11 +312,29 @@ void exynos4_restart(char mode, const char *cmd)
286 312
287void exynos5_restart(char mode, const char *cmd) 313void exynos5_restart(char mode, const char *cmd)
288{ 314{
289 __raw_writel(0x1, EXYNOS_SWRESET); 315 u32 val;
316 void __iomem *addr;
317
318 if (of_machine_is_compatible("samsung,exynos5250")) {
319 val = 0x1;
320 addr = EXYNOS_SWRESET;
321 } else if (of_machine_is_compatible("samsung,exynos5440")) {
322 val = (0x10 << 20) | (0x1 << 16);
323 addr = EXYNOS5440_SWRESET;
324 } else {
325 pr_err("%s: cannot support non-DT\n", __func__);
326 return;
327 }
328
329 __raw_writel(val, addr);
290} 330}
291 331
292void __init exynos_init_late(void) 332void __init exynos_init_late(void)
293{ 333{
334 if (of_machine_is_compatible("samsung,exynos5440"))
335 /* to be supported later */
336 return;
337
294 exynos_pm_late_initcall(); 338 exynos_pm_late_initcall();
295} 339}
296 340
@@ -303,7 +347,11 @@ void __init exynos_init_late(void)
303void __init exynos_init_io(struct map_desc *mach_desc, int size) 347void __init exynos_init_io(struct map_desc *mach_desc, int size)
304{ 348{
305 /* initialize the io descriptors we need for initialization */ 349 /* initialize the io descriptors we need for initialization */
306 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); 350 if (of_machine_is_compatible("samsung,exynos5440"))
351 iotable_init(exynos5440_iodesc, ARRAY_SIZE(exynos5440_iodesc));
352 else
353 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
354
307 if (mach_desc) 355 if (mach_desc)
308 iotable_init(mach_desc, size); 356 iotable_init(mach_desc, size);
309 357
@@ -389,6 +437,11 @@ static void __init exynos4_init_clocks(int xtal)
389 exynos4_setup_clocks(); 437 exynos4_setup_clocks();
390} 438}
391 439
440static void __init exynos5440_map_io(void)
441{
442 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
443}
444
392static void __init exynos5_init_clocks(int xtal) 445static void __init exynos5_init_clocks(int xtal)
393{ 446{
394 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 447 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -604,8 +657,9 @@ int __init combiner_of_init(struct device_node *np, struct device_node *parent)
604 return 0; 657 return 0;
605} 658}
606 659
607static const struct of_device_id exynos4_dt_irq_match[] = { 660static const struct of_device_id exynos_dt_irq_match[] = {
608 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 661 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
662 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
609 { .compatible = "samsung,exynos4210-combiner", 663 { .compatible = "samsung,exynos4210-combiner",
610 .data = combiner_of_init, }, 664 .data = combiner_of_init, },
611 {}, 665 {},
@@ -622,7 +676,7 @@ void __init exynos4_init_irq(void)
622 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); 676 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
623#ifdef CONFIG_OF 677#ifdef CONFIG_OF
624 else 678 else
625 of_irq_init(exynos4_dt_irq_match); 679 of_irq_init(exynos_dt_irq_match);
626#endif 680#endif
627 681
628 if (!of_have_populated_dt()) 682 if (!of_have_populated_dt())
@@ -639,7 +693,7 @@ void __init exynos4_init_irq(void)
639void __init exynos5_init_irq(void) 693void __init exynos5_init_irq(void)
640{ 694{
641#ifdef CONFIG_OF 695#ifdef CONFIG_OF
642 of_irq_init(exynos4_dt_irq_match); 696 of_irq_init(exynos_dt_irq_match);
643#endif 697#endif
644 /* 698 /*
645 * The parameters of s5p_init_irq() are for VIC init. 699 * The parameters of s5p_init_irq() are for VIC init.
@@ -669,7 +723,7 @@ static int __init exynos4_l2x0_cache_init(void)
669{ 723{
670 int ret; 724 int ret;
671 725
672 if (soc_is_exynos5250()) 726 if (soc_is_exynos5250() || soc_is_exynos5440())
673 return 0; 727 return 0;
674 728
675 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); 729 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
@@ -1010,6 +1064,8 @@ static int __init exynos_init_irq_eint(void)
1010 } 1064 }
1011 } 1065 }
1012#endif 1066#endif
1067 if (soc_is_exynos5440())
1068 return 0;
1013 1069
1014 if (soc_is_exynos5250()) 1070 if (soc_is_exynos5250())
1015 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); 1071 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);