diff options
author | Amit Daniel Kachhap <amit.kachhap@linaro.org> | 2012-03-08 05:09:12 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-09 10:04:51 -0500 |
commit | 6cdeddcc8149672d4b888709d063825a80304d09 (patch) | |
tree | 25d56df27ad372609e97bff02507f7fd54f295a3 /arch/arm/mach-exynos/common.c | |
parent | d0341c61a2f641c4f90f4ed4b0d538c9bcb63d18 (diff) |
ARM: EXYNOS: Enable l2 configuration through device tree
This patch enables calling generic l2 setup functions if device tree is used.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r-- | arch/arm/mach-exynos/common.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 9ff38aa08fd0..cb5ad8c1fea8 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -47,6 +47,8 @@ | |||
47 | #include <plat/regs-serial.h> | 47 | #include <plat/regs-serial.h> |
48 | 48 | ||
49 | #include "common.h" | 49 | #include "common.h" |
50 | #define L2_AUX_VAL 0x7C470001 | ||
51 | #define L2_AUX_MASK 0xC200ffff | ||
50 | 52 | ||
51 | static const char name_exynos4210[] = "EXYNOS4210"; | 53 | static const char name_exynos4210[] = "EXYNOS4210"; |
52 | static const char name_exynos4212[] = "EXYNOS4212"; | 54 | static const char name_exynos4212[] = "EXYNOS4212"; |
@@ -443,6 +445,14 @@ core_initcall(exynos4_core_init); | |||
443 | #ifdef CONFIG_CACHE_L2X0 | 445 | #ifdef CONFIG_CACHE_L2X0 |
444 | static int __init exynos4_l2x0_cache_init(void) | 446 | static int __init exynos4_l2x0_cache_init(void) |
445 | { | 447 | { |
448 | int ret; | ||
449 | ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); | ||
450 | if (!ret) { | ||
451 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); | ||
452 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
453 | return 0; | ||
454 | } | ||
455 | |||
446 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { | 456 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { |
447 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; | 457 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; |
448 | /* TAG, Data Latency Control: 2 cycles */ | 458 | /* TAG, Data Latency Control: 2 cycles */ |
@@ -476,8 +486,7 @@ static int __init exynos4_l2x0_cache_init(void) | |||
476 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); | 486 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); |
477 | } | 487 | } |
478 | 488 | ||
479 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); | 489 | l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); |
480 | |||
481 | return 0; | 490 | return 0; |
482 | } | 491 | } |
483 | 492 | ||