ARM: EXYNOS: Change System MMU platform device definitions

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 90 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982d0f8e..3320ad140ebe 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 }
 
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
                 .parent         = &exynos5_clk_aclk_66.clk,
                 .enable         = exynos5_clk_ip_peric_ctrl,
                 .ctrlbit        = (1 << 14),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+                .enable         = &exynos5_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+                .enable         = &exynos5_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
+                .enable         = &exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 9)
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+                .enable         = &exynos5_clk_ip_gen_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
+                .enable         = &exynos5_clk_ip_gen_ctrl,
+                .ctrlbit        = (1 << 6)
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .enable         = &exynos5_clk_ip_isp0_ctrl,
+                .ctrlbit        = (0x3F << 8),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME2,
+                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .enable         = &exynos5_clk_ip_isp1_ctrl,
+                .ctrlbit        = (0xF << 4),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
+                .enable         = &exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = SYSMMU_CLOCK_NAME,
+                .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
+                .enable         = &exynos5_clk_ip_acp_ctrl,
+                .ctrlbit        = (1 << 7)
         }
 };