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authorSachin Kamat <sachin.kamat@linaro.org>2012-07-16 18:52:03 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-07-16 18:52:03 -0400
commit6c6c185b45568dd3bc887d7248228476e3a6906a (patch)
treed20198de031dc6cd01752d48d521eff81ae7efc8 /arch/arm/mach-exynos/clock-exynos4212.c
parent8bf56466414aef011983d96ef401fe3ad75cfc29 (diff)
ARM: EXYNOS: Add G2D related clock entries for SMDK4X12
Adds G2D related clock entries for SMDK4X12 boards. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4212.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c41
1 files changed, 39 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index da397d21bbcf..8fba0b5fb8ab 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = {
68 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 }, 68 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
69}; 69};
70 70
71static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
72 .clk = {
73 .name = "mout_g2d0",
74 },
75 .sources = &exynos4_clkset_mout_g2d0,
76 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
77};
78
79static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
80 .clk = {
81 .name = "mout_g2d1",
82 },
83 .sources = &exynos4_clkset_mout_g2d1,
84 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
85};
86
87static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
88 [0] = &exynos4x12_clk_mout_g2d0.clk,
89 [1] = &exynos4x12_clk_mout_g2d1.clk,
90};
91
92static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
93 .sources = exynos4x12_clkset_mout_g2d_list,
94 .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
95};
96
71static struct clksrc_clk *sysclks[] = { 97static struct clksrc_clk *sysclks[] = {
72 &clk_mout_mpll_user, 98 &clk_mout_mpll_user,
73}; 99};
74 100
75static struct clksrc_clk clksrcs[] = { 101static struct clksrc_clk clksrcs[] = {
76 /* nothing here yet */ 102 {
103 .clk = {
104 .name = "sclk_fimg2d",
105 },
106 .sources = &exynos4x12_clkset_mout_g2d,
107 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
108 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
109 },
77}; 110};
78 111
79static struct clk init_clocks_off[] = { 112static struct clk init_clocks_off[] = {
@@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = {
102 .devname = "exynos-fimc-lite.1", 135 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl, 136 .enable = exynos4212_clk_ip_isp0_ctrl,
104 .ctrlbit = (1 << 3), 137 .ctrlbit = (1 << 3),
105 } 138 }, {
139 .name = "fimg2d",
140 .enable = exynos4_clk_ip_dmc_ctrl,
141 .ctrlbit = (1 << 23),
142 },
106}; 143};
107 144
108#ifdef CONFIG_PM_SLEEP 145#ifdef CONFIG_PM_SLEEP