ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock

This patch changes prefix of the clk register from S5P_ to
EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix
exynos4_ on clk declarations.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 21 insertions, 23 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 904240109d94..3b131e4b6ef5 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * EXYNOS4210 - Clock support
@@ -34,14 +32,14 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
 
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+                .sources = &exynos4_clkset_mout_corebus,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
                         .name           = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
         },
 };
 
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
         {
                 .name           = "sataphy",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "sata",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
         int ptr;
 
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-        clk_mout_mpll.reg_src.shift = 8;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+        exynos4_clk_mout_mpll.reg_src.shift = 8;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);