ARM: EXYNOS: remove system mmu initialization from exynos tree

This removes System MMU initialization from arch/arm/mach-exynos/
to move them to DT and the exynos-iommu driver except gating clock
definitions.

Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>

1 files changed, 20 insertions, 21 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bbcb3dea0d40..8a8468d83c8c 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,7 +24,6 @@
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
 
 #include "common.h"
 #include "clock-exynos4.h"
@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.0",
                 .enable         = exynos4_clk_ip_mfc_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.1",
                 .enable         = exynos4_clk_ip_mfc_ctrl,
                 .ctrlbit        = (1 << 2),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.2",
                 .enable         = exynos4_clk_ip_tv_ctrl,
                 .ctrlbit        = (1 << 4),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.3",
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 11),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.4",
                 .enable         = exynos4_clk_ip_image_ctrl,
                 .ctrlbit        = (1 << 4),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.5",
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.6",
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.7",
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.8",
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
-                .name           = SYSMMU_CLOCK_NAME,
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.10",
                 .enable         = exynos4_clk_ip_lcd0_ctrl,
                 .ctrlbit        = (1 << 4),
         }