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authorOlof Johansson <olof@lixom.net>2012-03-13 19:08:06 -0400
committerOlof Johansson <olof@lixom.net>2012-03-13 19:08:06 -0400
commite3643b77de143c5548ec93abd8aa68f4123295ea (patch)
tree41981957bc93e8211fe55cd04b7cac47e74bc770 /arch/arm/mach-exynos/clock-exynos4.c
parent86ca5b6fef2bf1aa77a62f29d844400e4fed8dde (diff)
parent44b2cef5ae6da48523fa634230ca66107110a7dd (diff)
Merge branch 'next/cleanup-exynos-clock' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
* 'next/cleanup-exynos-clock' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver ARM: EXYNOS: add clock registers for exynos4x12-cpufreq PM / devfreq: update the name of EXYNOS clock registers that were omitted PM / devfreq: update the name of EXYNOS clock register ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock ARM: EXYNOS: use static declaration on regarding clock ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs (includes an update to v3.3-rc6)
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1563
1 files changed, 1563 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 000000000000..31b59e65463a
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1563 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30#include "clock-exynos4.h"
31
32#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95};
96#endif
97
98static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m",
100 .rate = 27000000,
101};
102
103static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy",
105};
106
107static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0",
109 .rate = 27000000,
110};
111
112static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1",
114};
115
116static struct clk dummy_apb_pclk = {
117 .name = "apb_pclk",
118 .id = -1,
119};
120
121static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122{
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124}
125
126static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127{
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129}
130
131static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132{
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134}
135
136int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137{
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139}
140
141static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142{
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144}
145
146static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147{
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149}
150
151static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152{
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154}
155
156static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157{
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159}
160
161static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162{
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164}
165
166static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167{
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169}
170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174}
175
176static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177{
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179}
180
181int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182{
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184}
185
186int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187{
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189}
190
191static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192{
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194}
195
196static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197{
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199}
200
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202{
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204}
205
206static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
207{
208 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209}
210
211/* Core list of CMU_CPU side */
212
213static struct clksrc_clk exynos4_clk_mout_apll = {
214 .clk = {
215 .name = "mout_apll",
216 },
217 .sources = &clk_src_apll,
218 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219};
220
221static struct clksrc_clk exynos4_clk_sclk_apll = {
222 .clk = {
223 .name = "sclk_apll",
224 .parent = &exynos4_clk_mout_apll.clk,
225 },
226 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227};
228
229static struct clksrc_clk exynos4_clk_mout_epll = {
230 .clk = {
231 .name = "mout_epll",
232 },
233 .sources = &clk_src_epll,
234 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235};
236
237struct clksrc_clk exynos4_clk_mout_mpll = {
238 .clk = {
239 .name = "mout_mpll",
240 },
241 .sources = &clk_src_mpll,
242
243 /* reg_src will be added in each SoCs' clock */
244};
245
246static struct clk *exynos4_clkset_moutcore_list[] = {
247 [0] = &exynos4_clk_mout_apll.clk,
248 [1] = &exynos4_clk_mout_mpll.clk,
249};
250
251static struct clksrc_sources exynos4_clkset_moutcore = {
252 .sources = exynos4_clkset_moutcore_list,
253 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
254};
255
256static struct clksrc_clk exynos4_clk_moutcore = {
257 .clk = {
258 .name = "moutcore",
259 },
260 .sources = &exynos4_clkset_moutcore,
261 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262};
263
264static struct clksrc_clk exynos4_clk_coreclk = {
265 .clk = {
266 .name = "core_clk",
267 .parent = &exynos4_clk_moutcore.clk,
268 },
269 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270};
271
272static struct clksrc_clk exynos4_clk_armclk = {
273 .clk = {
274 .name = "armclk",
275 .parent = &exynos4_clk_coreclk.clk,
276 },
277};
278
279static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280 .clk = {
281 .name = "aclk_corem0",
282 .parent = &exynos4_clk_coreclk.clk,
283 },
284 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285};
286
287static struct clksrc_clk exynos4_clk_aclk_cores = {
288 .clk = {
289 .name = "aclk_cores",
290 .parent = &exynos4_clk_coreclk.clk,
291 },
292 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293};
294
295static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296 .clk = {
297 .name = "aclk_corem1",
298 .parent = &exynos4_clk_coreclk.clk,
299 },
300 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301};
302
303static struct clksrc_clk exynos4_clk_periphclk = {
304 .clk = {
305 .name = "periphclk",
306 .parent = &exynos4_clk_coreclk.clk,
307 },
308 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309};
310
311/* Core list of CMU_CORE side */
312
313static struct clk *exynos4_clkset_corebus_list[] = {
314 [0] = &exynos4_clk_mout_mpll.clk,
315 [1] = &exynos4_clk_sclk_apll.clk,
316};
317
318struct clksrc_sources exynos4_clkset_mout_corebus = {
319 .sources = exynos4_clkset_corebus_list,
320 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
321};
322
323static struct clksrc_clk exynos4_clk_mout_corebus = {
324 .clk = {
325 .name = "mout_corebus",
326 },
327 .sources = &exynos4_clkset_mout_corebus,
328 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329};
330
331static struct clksrc_clk exynos4_clk_sclk_dmc = {
332 .clk = {
333 .name = "sclk_dmc",
334 .parent = &exynos4_clk_mout_corebus.clk,
335 },
336 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337};
338
339static struct clksrc_clk exynos4_clk_aclk_cored = {
340 .clk = {
341 .name = "aclk_cored",
342 .parent = &exynos4_clk_sclk_dmc.clk,
343 },
344 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos4_clk_aclk_corep = {
348 .clk = {
349 .name = "aclk_corep",
350 .parent = &exynos4_clk_aclk_cored.clk,
351 },
352 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353};
354
355static struct clksrc_clk exynos4_clk_aclk_acp = {
356 .clk = {
357 .name = "aclk_acp",
358 .parent = &exynos4_clk_mout_corebus.clk,
359 },
360 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361};
362
363static struct clksrc_clk exynos4_clk_pclk_acp = {
364 .clk = {
365 .name = "pclk_acp",
366 .parent = &exynos4_clk_aclk_acp.clk,
367 },
368 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369};
370
371/* Core list of CMU_TOP side */
372
373struct clk *exynos4_clkset_aclk_top_list[] = {
374 [0] = &exynos4_clk_mout_mpll.clk,
375 [1] = &exynos4_clk_sclk_apll.clk,
376};
377
378static struct clksrc_sources exynos4_clkset_aclk = {
379 .sources = exynos4_clkset_aclk_top_list,
380 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381};
382
383static struct clksrc_clk exynos4_clk_aclk_200 = {
384 .clk = {
385 .name = "aclk_200",
386 },
387 .sources = &exynos4_clkset_aclk,
388 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
389 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390};
391
392static struct clksrc_clk exynos4_clk_aclk_100 = {
393 .clk = {
394 .name = "aclk_100",
395 },
396 .sources = &exynos4_clkset_aclk,
397 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
398 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399};
400
401static struct clksrc_clk exynos4_clk_aclk_160 = {
402 .clk = {
403 .name = "aclk_160",
404 },
405 .sources = &exynos4_clkset_aclk,
406 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
407 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408};
409
410struct clksrc_clk exynos4_clk_aclk_133 = {
411 .clk = {
412 .name = "aclk_133",
413 },
414 .sources = &exynos4_clkset_aclk,
415 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
416 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417};
418
419static struct clk *exynos4_clkset_vpllsrc_list[] = {
420 [0] = &clk_fin_vpll,
421 [1] = &exynos4_clk_sclk_hdmi27m,
422};
423
424static struct clksrc_sources exynos4_clkset_vpllsrc = {
425 .sources = exynos4_clkset_vpllsrc_list,
426 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427};
428
429static struct clksrc_clk exynos4_clk_vpllsrc = {
430 .clk = {
431 .name = "vpll_src",
432 .enable = exynos4_clksrc_mask_top_ctrl,
433 .ctrlbit = (1 << 0),
434 },
435 .sources = &exynos4_clkset_vpllsrc,
436 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437};
438
439static struct clk *exynos4_clkset_sclk_vpll_list[] = {
440 [0] = &exynos4_clk_vpllsrc.clk,
441 [1] = &clk_fout_vpll,
442};
443
444static struct clksrc_sources exynos4_clkset_sclk_vpll = {
445 .sources = exynos4_clkset_sclk_vpll_list,
446 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447};
448
449static struct clksrc_clk exynos4_clk_sclk_vpll = {
450 .clk = {
451 .name = "sclk_vpll",
452 },
453 .sources = &exynos4_clkset_sclk_vpll,
454 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455};
456
457static struct clk exynos4_init_clocks_off[] = {
458 {
459 .name = "timers",
460 .parent = &exynos4_clk_aclk_100.clk,
461 .enable = exynos4_clk_ip_peril_ctrl,
462 .ctrlbit = (1<<24),
463 }, {
464 .name = "csis",
465 .devname = "s5p-mipi-csis.0",
466 .enable = exynos4_clk_ip_cam_ctrl,
467 .ctrlbit = (1 << 4),
468 }, {
469 .name = "csis",
470 .devname = "s5p-mipi-csis.1",
471 .enable = exynos4_clk_ip_cam_ctrl,
472 .ctrlbit = (1 << 5),
473 }, {
474 .name = "fimc",
475 .devname = "exynos4-fimc.0",
476 .enable = exynos4_clk_ip_cam_ctrl,
477 .ctrlbit = (1 << 0),
478 }, {
479 .name = "fimc",
480 .devname = "exynos4-fimc.1",
481 .enable = exynos4_clk_ip_cam_ctrl,
482 .ctrlbit = (1 << 1),
483 }, {
484 .name = "fimc",
485 .devname = "exynos4-fimc.2",
486 .enable = exynos4_clk_ip_cam_ctrl,
487 .ctrlbit = (1 << 2),
488 }, {
489 .name = "fimc",
490 .devname = "exynos4-fimc.3",
491 .enable = exynos4_clk_ip_cam_ctrl,
492 .ctrlbit = (1 << 3),
493 }, {
494 .name = "fimd",
495 .devname = "exynos4-fb.0",
496 .enable = exynos4_clk_ip_lcd0_ctrl,
497 .ctrlbit = (1 << 0),
498 }, {
499 .name = "hsmmc",
500 .devname = "s3c-sdhci.0",
501 .parent = &exynos4_clk_aclk_133.clk,
502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 5),
504 }, {
505 .name = "hsmmc",
506 .devname = "s3c-sdhci.1",
507 .parent = &exynos4_clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl,
509 .ctrlbit = (1 << 6),
510 }, {
511 .name = "hsmmc",
512 .devname = "s3c-sdhci.2",
513 .parent = &exynos4_clk_aclk_133.clk,
514 .enable = exynos4_clk_ip_fsys_ctrl,
515 .ctrlbit = (1 << 7),
516 }, {
517 .name = "hsmmc",
518 .devname = "s3c-sdhci.3",
519 .parent = &exynos4_clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl,
521 .ctrlbit = (1 << 8),
522 }, {
523 .name = "dwmmc",
524 .parent = &exynos4_clk_aclk_133.clk,
525 .enable = exynos4_clk_ip_fsys_ctrl,
526 .ctrlbit = (1 << 9),
527 }, {
528 .name = "dac",
529 .devname = "s5p-sdo",
530 .enable = exynos4_clk_ip_tv_ctrl,
531 .ctrlbit = (1 << 2),
532 }, {
533 .name = "mixer",
534 .devname = "s5p-mixer",
535 .enable = exynos4_clk_ip_tv_ctrl,
536 .ctrlbit = (1 << 1),
537 }, {
538 .name = "vp",
539 .devname = "s5p-mixer",
540 .enable = exynos4_clk_ip_tv_ctrl,
541 .ctrlbit = (1 << 0),
542 }, {
543 .name = "hdmi",
544 .devname = "exynos4-hdmi",
545 .enable = exynos4_clk_ip_tv_ctrl,
546 .ctrlbit = (1 << 3),
547 }, {
548 .name = "hdmiphy",
549 .devname = "exynos4-hdmi",
550 .enable = exynos4_clk_hdmiphy_ctrl,
551 .ctrlbit = (1 << 0),
552 }, {
553 .name = "dacphy",
554 .devname = "s5p-sdo",
555 .enable = exynos4_clk_dac_ctrl,
556 .ctrlbit = (1 << 0),
557 }, {
558 .name = "adc",
559 .enable = exynos4_clk_ip_peril_ctrl,
560 .ctrlbit = (1 << 15),
561 }, {
562 .name = "keypad",
563 .enable = exynos4_clk_ip_perir_ctrl,
564 .ctrlbit = (1 << 16),
565 }, {
566 .name = "rtc",
567 .enable = exynos4_clk_ip_perir_ctrl,
568 .ctrlbit = (1 << 15),
569 }, {
570 .name = "watchdog",
571 .parent = &exynos4_clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_perir_ctrl,
573 .ctrlbit = (1 << 14),
574 }, {
575 .name = "usbhost",
576 .enable = exynos4_clk_ip_fsys_ctrl ,
577 .ctrlbit = (1 << 12),
578 }, {
579 .name = "otg",
580 .enable = exynos4_clk_ip_fsys_ctrl,
581 .ctrlbit = (1 << 13),
582 }, {
583 .name = "spi",
584 .devname = "s3c64xx-spi.0",
585 .enable = exynos4_clk_ip_peril_ctrl,
586 .ctrlbit = (1 << 16),
587 }, {
588 .name = "spi",
589 .devname = "s3c64xx-spi.1",
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 17),
592 }, {
593 .name = "spi",
594 .devname = "s3c64xx-spi.2",
595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 18),
597 }, {
598 .name = "iis",
599 .devname = "samsung-i2s.0",
600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 19),
602 }, {
603 .name = "iis",
604 .devname = "samsung-i2s.1",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 20),
607 }, {
608 .name = "iis",
609 .devname = "samsung-i2s.2",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 21),
612 }, {
613 .name = "ac97",
614 .devname = "samsung-ac97",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 27),
617 }, {
618 .name = "fimg2d",
619 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 0),
621 }, {
622 .name = "mfc",
623 .devname = "s5p-mfc",
624 .enable = exynos4_clk_ip_mfc_ctrl,
625 .ctrlbit = (1 << 0),
626 }, {
627 .name = "i2c",
628 .devname = "s3c2440-i2c.0",
629 .parent = &exynos4_clk_aclk_100.clk,
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 6),
632 }, {
633 .name = "i2c",
634 .devname = "s3c2440-i2c.1",
635 .parent = &exynos4_clk_aclk_100.clk,
636 .enable = exynos4_clk_ip_peril_ctrl,
637 .ctrlbit = (1 << 7),
638 }, {
639 .name = "i2c",
640 .devname = "s3c2440-i2c.2",
641 .parent = &exynos4_clk_aclk_100.clk,
642 .enable = exynos4_clk_ip_peril_ctrl,
643 .ctrlbit = (1 << 8),
644 }, {
645 .name = "i2c",
646 .devname = "s3c2440-i2c.3",
647 .parent = &exynos4_clk_aclk_100.clk,
648 .enable = exynos4_clk_ip_peril_ctrl,
649 .ctrlbit = (1 << 9),
650 }, {
651 .name = "i2c",
652 .devname = "s3c2440-i2c.4",
653 .parent = &exynos4_clk_aclk_100.clk,
654 .enable = exynos4_clk_ip_peril_ctrl,
655 .ctrlbit = (1 << 10),
656 }, {
657 .name = "i2c",
658 .devname = "s3c2440-i2c.5",
659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 11),
662 }, {
663 .name = "i2c",
664 .devname = "s3c2440-i2c.6",
665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 12),
668 }, {
669 .name = "i2c",
670 .devname = "s3c2440-i2c.7",
671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 13),
674 }, {
675 .name = "i2c",
676 .devname = "s3c2440-hdmiphy-i2c",
677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 14),
680 }, {
681 .name = "SYSMMU_MDMA",
682 .enable = exynos4_clk_ip_image_ctrl,
683 .ctrlbit = (1 << 5),
684 }, {
685 .name = "SYSMMU_FIMC0",
686 .enable = exynos4_clk_ip_cam_ctrl,
687 .ctrlbit = (1 << 7),
688 }, {
689 .name = "SYSMMU_FIMC1",
690 .enable = exynos4_clk_ip_cam_ctrl,
691 .ctrlbit = (1 << 8),
692 }, {
693 .name = "SYSMMU_FIMC2",
694 .enable = exynos4_clk_ip_cam_ctrl,
695 .ctrlbit = (1 << 9),
696 }, {
697 .name = "SYSMMU_FIMC3",
698 .enable = exynos4_clk_ip_cam_ctrl,
699 .ctrlbit = (1 << 10),
700 }, {
701 .name = "SYSMMU_JPEG",
702 .enable = exynos4_clk_ip_cam_ctrl,
703 .ctrlbit = (1 << 11),
704 }, {
705 .name = "SYSMMU_FIMD0",
706 .enable = exynos4_clk_ip_lcd0_ctrl,
707 .ctrlbit = (1 << 4),
708 }, {
709 .name = "SYSMMU_FIMD1",
710 .enable = exynos4_clk_ip_lcd1_ctrl,
711 .ctrlbit = (1 << 4),
712 }, {
713 .name = "SYSMMU_PCIe",
714 .enable = exynos4_clk_ip_fsys_ctrl,
715 .ctrlbit = (1 << 18),
716 }, {
717 .name = "SYSMMU_G2D",
718 .enable = exynos4_clk_ip_image_ctrl,
719 .ctrlbit = (1 << 3),
720 }, {
721 .name = "SYSMMU_ROTATOR",
722 .enable = exynos4_clk_ip_image_ctrl,
723 .ctrlbit = (1 << 4),
724 }, {
725 .name = "SYSMMU_TV",
726 .enable = exynos4_clk_ip_tv_ctrl,
727 .ctrlbit = (1 << 4),
728 }, {
729 .name = "SYSMMU_MFC_L",
730 .enable = exynos4_clk_ip_mfc_ctrl,
731 .ctrlbit = (1 << 1),
732 }, {
733 .name = "SYSMMU_MFC_R",
734 .enable = exynos4_clk_ip_mfc_ctrl,
735 .ctrlbit = (1 << 2),
736 }
737};
738
739static struct clk exynos4_init_clocks_on[] = {
740 {
741 .name = "uart",
742 .devname = "s5pv210-uart.0",
743 .enable = exynos4_clk_ip_peril_ctrl,
744 .ctrlbit = (1 << 0),
745 }, {
746 .name = "uart",
747 .devname = "s5pv210-uart.1",
748 .enable = exynos4_clk_ip_peril_ctrl,
749 .ctrlbit = (1 << 1),
750 }, {
751 .name = "uart",
752 .devname = "s5pv210-uart.2",
753 .enable = exynos4_clk_ip_peril_ctrl,
754 .ctrlbit = (1 << 2),
755 }, {
756 .name = "uart",
757 .devname = "s5pv210-uart.3",
758 .enable = exynos4_clk_ip_peril_ctrl,
759 .ctrlbit = (1 << 3),
760 }, {
761 .name = "uart",
762 .devname = "s5pv210-uart.4",
763 .enable = exynos4_clk_ip_peril_ctrl,
764 .ctrlbit = (1 << 4),
765 }, {
766 .name = "uart",
767 .devname = "s5pv210-uart.5",
768 .enable = exynos4_clk_ip_peril_ctrl,
769 .ctrlbit = (1 << 5),
770 }
771};
772
773static struct clk exynos4_clk_pdma0 = {
774 .name = "dma",
775 .devname = "dma-pl330.0",
776 .enable = exynos4_clk_ip_fsys_ctrl,
777 .ctrlbit = (1 << 0),
778};
779
780static struct clk exynos4_clk_pdma1 = {
781 .name = "dma",
782 .devname = "dma-pl330.1",
783 .enable = exynos4_clk_ip_fsys_ctrl,
784 .ctrlbit = (1 << 1),
785};
786
787struct clk *exynos4_clkset_group_list[] = {
788 [0] = &clk_ext_xtal_mux,
789 [1] = &clk_xusbxti,
790 [2] = &exynos4_clk_sclk_hdmi27m,
791 [3] = &exynos4_clk_sclk_usbphy0,
792 [4] = &exynos4_clk_sclk_usbphy1,
793 [5] = &exynos4_clk_sclk_hdmiphy,
794 [6] = &exynos4_clk_mout_mpll.clk,
795 [7] = &exynos4_clk_mout_epll.clk,
796 [8] = &exynos4_clk_sclk_vpll.clk,
797};
798
799struct clksrc_sources exynos4_clkset_group = {
800 .sources = exynos4_clkset_group_list,
801 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
802};
803
804static struct clk *exynos4_clkset_mout_g2d0_list[] = {
805 [0] = &exynos4_clk_mout_mpll.clk,
806 [1] = &exynos4_clk_sclk_apll.clk,
807};
808
809static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
810 .sources = exynos4_clkset_mout_g2d0_list,
811 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
812};
813
814static struct clksrc_clk exynos4_clk_mout_g2d0 = {
815 .clk = {
816 .name = "mout_g2d0",
817 },
818 .sources = &exynos4_clkset_mout_g2d0,
819 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
820};
821
822static struct clk *exynos4_clkset_mout_g2d1_list[] = {
823 [0] = &exynos4_clk_mout_epll.clk,
824 [1] = &exynos4_clk_sclk_vpll.clk,
825};
826
827static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
828 .sources = exynos4_clkset_mout_g2d1_list,
829 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
830};
831
832static struct clksrc_clk exynos4_clk_mout_g2d1 = {
833 .clk = {
834 .name = "mout_g2d1",
835 },
836 .sources = &exynos4_clkset_mout_g2d1,
837 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
838};
839
840static struct clk *exynos4_clkset_mout_g2d_list[] = {
841 [0] = &exynos4_clk_mout_g2d0.clk,
842 [1] = &exynos4_clk_mout_g2d1.clk,
843};
844
845static struct clksrc_sources exynos4_clkset_mout_g2d = {
846 .sources = exynos4_clkset_mout_g2d_list,
847 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
848};
849
850static struct clk *exynos4_clkset_mout_mfc0_list[] = {
851 [0] = &exynos4_clk_mout_mpll.clk,
852 [1] = &exynos4_clk_sclk_apll.clk,
853};
854
855static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
856 .sources = exynos4_clkset_mout_mfc0_list,
857 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
858};
859
860static struct clksrc_clk exynos4_clk_mout_mfc0 = {
861 .clk = {
862 .name = "mout_mfc0",
863 },
864 .sources = &exynos4_clkset_mout_mfc0,
865 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
866};
867
868static struct clk *exynos4_clkset_mout_mfc1_list[] = {
869 [0] = &exynos4_clk_mout_epll.clk,
870 [1] = &exynos4_clk_sclk_vpll.clk,
871};
872
873static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
874 .sources = exynos4_clkset_mout_mfc1_list,
875 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
876};
877
878static struct clksrc_clk exynos4_clk_mout_mfc1 = {
879 .clk = {
880 .name = "mout_mfc1",
881 },
882 .sources = &exynos4_clkset_mout_mfc1,
883 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
884};
885
886static struct clk *exynos4_clkset_mout_mfc_list[] = {
887 [0] = &exynos4_clk_mout_mfc0.clk,
888 [1] = &exynos4_clk_mout_mfc1.clk,
889};
890
891static struct clksrc_sources exynos4_clkset_mout_mfc = {
892 .sources = exynos4_clkset_mout_mfc_list,
893 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
894};
895
896static struct clk *exynos4_clkset_sclk_dac_list[] = {
897 [0] = &exynos4_clk_sclk_vpll.clk,
898 [1] = &exynos4_clk_sclk_hdmiphy,
899};
900
901static struct clksrc_sources exynos4_clkset_sclk_dac = {
902 .sources = exynos4_clkset_sclk_dac_list,
903 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
904};
905
906static struct clksrc_clk exynos4_clk_sclk_dac = {
907 .clk = {
908 .name = "sclk_dac",
909 .enable = exynos4_clksrc_mask_tv_ctrl,
910 .ctrlbit = (1 << 8),
911 },
912 .sources = &exynos4_clkset_sclk_dac,
913 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
914};
915
916static struct clksrc_clk exynos4_clk_sclk_pixel = {
917 .clk = {
918 .name = "sclk_pixel",
919 .parent = &exynos4_clk_sclk_vpll.clk,
920 },
921 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
922};
923
924static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
925 [0] = &exynos4_clk_sclk_pixel.clk,
926 [1] = &exynos4_clk_sclk_hdmiphy,
927};
928
929static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
930 .sources = exynos4_clkset_sclk_hdmi_list,
931 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
932};
933
934static struct clksrc_clk exynos4_clk_sclk_hdmi = {
935 .clk = {
936 .name = "sclk_hdmi",
937 .enable = exynos4_clksrc_mask_tv_ctrl,
938 .ctrlbit = (1 << 0),
939 },
940 .sources = &exynos4_clkset_sclk_hdmi,
941 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
942};
943
944static struct clk *exynos4_clkset_sclk_mixer_list[] = {
945 [0] = &exynos4_clk_sclk_dac.clk,
946 [1] = &exynos4_clk_sclk_hdmi.clk,
947};
948
949static struct clksrc_sources exynos4_clkset_sclk_mixer = {
950 .sources = exynos4_clkset_sclk_mixer_list,
951 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
952};
953
954static struct clksrc_clk exynos4_clk_sclk_mixer = {
955 .clk = {
956 .name = "sclk_mixer",
957 .enable = exynos4_clksrc_mask_tv_ctrl,
958 .ctrlbit = (1 << 4),
959 },
960 .sources = &exynos4_clkset_sclk_mixer,
961 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
962};
963
964static struct clksrc_clk *exynos4_sclk_tv[] = {
965 &exynos4_clk_sclk_dac,
966 &exynos4_clk_sclk_pixel,
967 &exynos4_clk_sclk_hdmi,
968 &exynos4_clk_sclk_mixer,
969};
970
971static struct clksrc_clk exynos4_clk_dout_mmc0 = {
972 .clk = {
973 .name = "dout_mmc0",
974 },
975 .sources = &exynos4_clkset_group,
976 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
977 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
978};
979
980static struct clksrc_clk exynos4_clk_dout_mmc1 = {
981 .clk = {
982 .name = "dout_mmc1",
983 },
984 .sources = &exynos4_clkset_group,
985 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
986 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
987};
988
989static struct clksrc_clk exynos4_clk_dout_mmc2 = {
990 .clk = {
991 .name = "dout_mmc2",
992 },
993 .sources = &exynos4_clkset_group,
994 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
995 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
996};
997
998static struct clksrc_clk exynos4_clk_dout_mmc3 = {
999 .clk = {
1000 .name = "dout_mmc3",
1001 },
1002 .sources = &exynos4_clkset_group,
1003 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1004 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1005};
1006
1007static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1008 .clk = {
1009 .name = "dout_mmc4",
1010 },
1011 .sources = &exynos4_clkset_group,
1012 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1013 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1014};
1015
1016static struct clksrc_clk exynos4_clksrcs[] = {
1017 {
1018 .clk = {
1019 .name = "sclk_pwm",
1020 .enable = exynos4_clksrc_mask_peril0_ctrl,
1021 .ctrlbit = (1 << 24),
1022 },
1023 .sources = &exynos4_clkset_group,
1024 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1025 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1026 }, {
1027 .clk = {
1028 .name = "sclk_csis",
1029 .devname = "s5p-mipi-csis.0",
1030 .enable = exynos4_clksrc_mask_cam_ctrl,
1031 .ctrlbit = (1 << 24),
1032 },
1033 .sources = &exynos4_clkset_group,
1034 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1035 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1036 }, {
1037 .clk = {
1038 .name = "sclk_csis",
1039 .devname = "s5p-mipi-csis.1",
1040 .enable = exynos4_clksrc_mask_cam_ctrl,
1041 .ctrlbit = (1 << 28),
1042 },
1043 .sources = &exynos4_clkset_group,
1044 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1045 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1046 }, {
1047 .clk = {
1048 .name = "sclk_cam0",
1049 .enable = exynos4_clksrc_mask_cam_ctrl,
1050 .ctrlbit = (1 << 16),
1051 },
1052 .sources = &exynos4_clkset_group,
1053 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1054 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1055 }, {
1056 .clk = {
1057 .name = "sclk_cam1",
1058 .enable = exynos4_clksrc_mask_cam_ctrl,
1059 .ctrlbit = (1 << 20),
1060 },
1061 .sources = &exynos4_clkset_group,
1062 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1063 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1064 }, {
1065 .clk = {
1066 .name = "sclk_fimc",
1067 .devname = "exynos4-fimc.0",
1068 .enable = exynos4_clksrc_mask_cam_ctrl,
1069 .ctrlbit = (1 << 0),
1070 },
1071 .sources = &exynos4_clkset_group,
1072 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1073 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1074 }, {
1075 .clk = {
1076 .name = "sclk_fimc",
1077 .devname = "exynos4-fimc.1",
1078 .enable = exynos4_clksrc_mask_cam_ctrl,
1079 .ctrlbit = (1 << 4),
1080 },
1081 .sources = &exynos4_clkset_group,
1082 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1083 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1084 }, {
1085 .clk = {
1086 .name = "sclk_fimc",
1087 .devname = "exynos4-fimc.2",
1088 .enable = exynos4_clksrc_mask_cam_ctrl,
1089 .ctrlbit = (1 << 8),
1090 },
1091 .sources = &exynos4_clkset_group,
1092 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1093 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1094 }, {
1095 .clk = {
1096 .name = "sclk_fimc",
1097 .devname = "exynos4-fimc.3",
1098 .enable = exynos4_clksrc_mask_cam_ctrl,
1099 .ctrlbit = (1 << 12),
1100 },
1101 .sources = &exynos4_clkset_group,
1102 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1103 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1104 }, {
1105 .clk = {
1106 .name = "sclk_fimd",
1107 .devname = "exynos4-fb.0",
1108 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1109 .ctrlbit = (1 << 0),
1110 },
1111 .sources = &exynos4_clkset_group,
1112 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1113 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1114 }, {
1115 .clk = {
1116 .name = "sclk_fimg2d",
1117 },
1118 .sources = &exynos4_clkset_mout_g2d,
1119 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1120 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1121 }, {
1122 .clk = {
1123 .name = "sclk_mfc",
1124 .devname = "s5p-mfc",
1125 },
1126 .sources = &exynos4_clkset_mout_mfc,
1127 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1128 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1129 }, {
1130 .clk = {
1131 .name = "sclk_dwmmc",
1132 .parent = &exynos4_clk_dout_mmc4.clk,
1133 .enable = exynos4_clksrc_mask_fsys_ctrl,
1134 .ctrlbit = (1 << 16),
1135 },
1136 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1137 }
1138};
1139
1140static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1141 .clk = {
1142 .name = "uclk1",
1143 .devname = "exynos4210-uart.0",
1144 .enable = exynos4_clksrc_mask_peril0_ctrl,
1145 .ctrlbit = (1 << 0),
1146 },
1147 .sources = &exynos4_clkset_group,
1148 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1149 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1150};
1151
1152static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1153 .clk = {
1154 .name = "uclk1",
1155 .devname = "exynos4210-uart.1",
1156 .enable = exynos4_clksrc_mask_peril0_ctrl,
1157 .ctrlbit = (1 << 4),
1158 },
1159 .sources = &exynos4_clkset_group,
1160 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1161 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1162};
1163
1164static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1165 .clk = {
1166 .name = "uclk1",
1167 .devname = "exynos4210-uart.2",
1168 .enable = exynos4_clksrc_mask_peril0_ctrl,
1169 .ctrlbit = (1 << 8),
1170 },
1171 .sources = &exynos4_clkset_group,
1172 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1173 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1174};
1175
1176static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1177 .clk = {
1178 .name = "uclk1",
1179 .devname = "exynos4210-uart.3",
1180 .enable = exynos4_clksrc_mask_peril0_ctrl,
1181 .ctrlbit = (1 << 12),
1182 },
1183 .sources = &exynos4_clkset_group,
1184 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1185 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1186};
1187
1188static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1189 .clk = {
1190 .name = "sclk_mmc",
1191 .devname = "s3c-sdhci.0",
1192 .parent = &exynos4_clk_dout_mmc0.clk,
1193 .enable = exynos4_clksrc_mask_fsys_ctrl,
1194 .ctrlbit = (1 << 0),
1195 },
1196 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1197};
1198
1199static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1200 .clk = {
1201 .name = "sclk_mmc",
1202 .devname = "s3c-sdhci.1",
1203 .parent = &exynos4_clk_dout_mmc1.clk,
1204 .enable = exynos4_clksrc_mask_fsys_ctrl,
1205 .ctrlbit = (1 << 4),
1206 },
1207 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1208};
1209
1210static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1211 .clk = {
1212 .name = "sclk_mmc",
1213 .devname = "s3c-sdhci.2",
1214 .parent = &exynos4_clk_dout_mmc2.clk,
1215 .enable = exynos4_clksrc_mask_fsys_ctrl,
1216 .ctrlbit = (1 << 8),
1217 },
1218 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1219};
1220
1221static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1222 .clk = {
1223 .name = "sclk_mmc",
1224 .devname = "s3c-sdhci.3",
1225 .parent = &exynos4_clk_dout_mmc3.clk,
1226 .enable = exynos4_clksrc_mask_fsys_ctrl,
1227 .ctrlbit = (1 << 12),
1228 },
1229 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1230};
1231
1232static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1233 .clk = {
1234 .name = "sclk_spi",
1235 .devname = "s3c64xx-spi.0",
1236 .enable = exynos4_clksrc_mask_peril1_ctrl,
1237 .ctrlbit = (1 << 16),
1238 },
1239 .sources = &exynos4_clkset_group,
1240 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1241 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1242};
1243
1244static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1245 .clk = {
1246 .name = "sclk_spi",
1247 .devname = "s3c64xx-spi.1",
1248 .enable = exynos4_clksrc_mask_peril1_ctrl,
1249 .ctrlbit = (1 << 20),
1250 },
1251 .sources = &exynos4_clkset_group,
1252 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1253 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1254};
1255
1256static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1257 .clk = {
1258 .name = "sclk_spi",
1259 .devname = "s3c64xx-spi.2",
1260 .enable = exynos4_clksrc_mask_peril1_ctrl,
1261 .ctrlbit = (1 << 24),
1262 },
1263 .sources = &exynos4_clkset_group,
1264 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1265 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1266};
1267
1268/* Clock initialization code */
1269static struct clksrc_clk *exynos4_sysclks[] = {
1270 &exynos4_clk_mout_apll,
1271 &exynos4_clk_sclk_apll,
1272 &exynos4_clk_mout_epll,
1273 &exynos4_clk_mout_mpll,
1274 &exynos4_clk_moutcore,
1275 &exynos4_clk_coreclk,
1276 &exynos4_clk_armclk,
1277 &exynos4_clk_aclk_corem0,
1278 &exynos4_clk_aclk_cores,
1279 &exynos4_clk_aclk_corem1,
1280 &exynos4_clk_periphclk,
1281 &exynos4_clk_mout_corebus,
1282 &exynos4_clk_sclk_dmc,
1283 &exynos4_clk_aclk_cored,
1284 &exynos4_clk_aclk_corep,
1285 &exynos4_clk_aclk_acp,
1286 &exynos4_clk_pclk_acp,
1287 &exynos4_clk_vpllsrc,
1288 &exynos4_clk_sclk_vpll,
1289 &exynos4_clk_aclk_200,
1290 &exynos4_clk_aclk_100,
1291 &exynos4_clk_aclk_160,
1292 &exynos4_clk_aclk_133,
1293 &exynos4_clk_dout_mmc0,
1294 &exynos4_clk_dout_mmc1,
1295 &exynos4_clk_dout_mmc2,
1296 &exynos4_clk_dout_mmc3,
1297 &exynos4_clk_dout_mmc4,
1298 &exynos4_clk_mout_mfc0,
1299 &exynos4_clk_mout_mfc1,
1300};
1301
1302static struct clk *exynos4_clk_cdev[] = {
1303 &exynos4_clk_pdma0,
1304 &exynos4_clk_pdma1,
1305};
1306
1307static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1308 &exynos4_clk_sclk_uart0,
1309 &exynos4_clk_sclk_uart1,
1310 &exynos4_clk_sclk_uart2,
1311 &exynos4_clk_sclk_uart3,
1312 &exynos4_clk_sclk_mmc0,
1313 &exynos4_clk_sclk_mmc1,
1314 &exynos4_clk_sclk_mmc2,
1315 &exynos4_clk_sclk_mmc3,
1316 &exynos4_clk_sclk_spi0,
1317 &exynos4_clk_sclk_spi1,
1318 &exynos4_clk_sclk_spi2,
1319
1320};
1321
1322static struct clk_lookup exynos4_clk_lookup[] = {
1323 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1324 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1325 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1326 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1327 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1328 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1329 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1330 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1331 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1332 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1333 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1334 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1335 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1336};
1337
1338static int xtal_rate;
1339
1340static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1341{
1342 if (soc_is_exynos4210())
1343 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1344 pll_4508);
1345 else if (soc_is_exynos4212() || soc_is_exynos4412())
1346 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1347 else
1348 return 0;
1349}
1350
1351static struct clk_ops exynos4_fout_apll_ops = {
1352 .get_rate = exynos4_fout_apll_get_rate,
1353};
1354
1355static u32 exynos4_vpll_div[][8] = {
1356 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1357 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1358};
1359
1360static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1361{
1362 return clk->rate;
1363}
1364
1365static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1366{
1367 unsigned int vpll_con0, vpll_con1 = 0;
1368 unsigned int i;
1369
1370 /* Return if nothing changed */
1371 if (clk->rate == rate)
1372 return 0;
1373
1374 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1375 vpll_con0 &= ~(0x1 << 27 | \
1376 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1377 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1378 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1379
1380 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1381 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1382 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1383 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1384
1385 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1386 if (exynos4_vpll_div[i][0] == rate) {
1387 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1388 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1389 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1390 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1391 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1392 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1393 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1394 break;
1395 }
1396 }
1397
1398 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1399 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1400 __func__);
1401 return -EINVAL;
1402 }
1403
1404 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1405 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1406
1407 /* Wait for VPLL lock */
1408 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1409 continue;
1410
1411 clk->rate = rate;
1412 return 0;
1413}
1414
1415static struct clk_ops exynos4_vpll_ops = {
1416 .get_rate = exynos4_vpll_get_rate,
1417 .set_rate = exynos4_vpll_set_rate,
1418};
1419
1420void __init_or_cpufreq exynos4_setup_clocks(void)
1421{
1422 struct clk *xtal_clk;
1423 unsigned long apll = 0;
1424 unsigned long mpll = 0;
1425 unsigned long epll = 0;
1426 unsigned long vpll = 0;
1427 unsigned long vpllsrc;
1428 unsigned long xtal;
1429 unsigned long armclk;
1430 unsigned long sclk_dmc;
1431 unsigned long aclk_200;
1432 unsigned long aclk_100;
1433 unsigned long aclk_160;
1434 unsigned long aclk_133;
1435 unsigned int ptr;
1436
1437 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1438
1439 xtal_clk = clk_get(NULL, "xtal");
1440 BUG_ON(IS_ERR(xtal_clk));
1441
1442 xtal = clk_get_rate(xtal_clk);
1443
1444 xtal_rate = xtal;
1445
1446 clk_put(xtal_clk);
1447
1448 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1449
1450 if (soc_is_exynos4210()) {
1451 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1452 pll_4508);
1453 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1454 pll_4508);
1455 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1456 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1457
1458 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1459 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1460 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1461 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1462 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1463 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1464 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1465 __raw_readl(EXYNOS4_EPLL_CON1));
1466
1467 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1468 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1469 __raw_readl(EXYNOS4_VPLL_CON1));
1470 } else {
1471 /* nothing */
1472 }
1473
1474 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1475 clk_fout_mpll.rate = mpll;
1476 clk_fout_epll.rate = epll;
1477 clk_fout_vpll.ops = &exynos4_vpll_ops;
1478 clk_fout_vpll.rate = vpll;
1479
1480 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1481 apll, mpll, epll, vpll);
1482
1483 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1484 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1485
1486 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1487 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1488 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1489 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1490
1491 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1492 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1493 armclk, sclk_dmc, aclk_200,
1494 aclk_100, aclk_160, aclk_133);
1495
1496 clk_f.rate = armclk;
1497 clk_h.rate = sclk_dmc;
1498 clk_p.rate = aclk_100;
1499
1500 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1501 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1502}
1503
1504static struct clk *exynos4_clks[] __initdata = {
1505 &exynos4_clk_sclk_hdmi27m,
1506 &exynos4_clk_sclk_hdmiphy,
1507 &exynos4_clk_sclk_usbphy0,
1508 &exynos4_clk_sclk_usbphy1,
1509};
1510
1511#ifdef CONFIG_PM_SLEEP
1512static int exynos4_clock_suspend(void)
1513{
1514 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1515 return 0;
1516}
1517
1518static void exynos4_clock_resume(void)
1519{
1520 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1521}
1522
1523#else
1524#define exynos4_clock_suspend NULL
1525#define exynos4_clock_resume NULL
1526#endif
1527
1528static struct syscore_ops exynos4_clock_syscore_ops = {
1529 .suspend = exynos4_clock_suspend,
1530 .resume = exynos4_clock_resume,
1531};
1532
1533void __init exynos4_register_clocks(void)
1534{
1535 int ptr;
1536
1537 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1538
1539 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1540 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1541
1542 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1543 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1544
1545 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1546 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1547
1548 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1549 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1550
1551 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1552 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1553 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1554
1555 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1556 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1557 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1558
1559 register_syscore_ops(&exynos4_clock_syscore_ops);
1560 s3c24xx_register_clock(&dummy_apb_pclk);
1561
1562 s3c_pwmclk_init();
1563}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 15:02:43 -0500