aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ep93xx/include
diff options
context:
space:
mode:
authorHartley Sweeten <hartleys@visionengravers.com>2009-06-30 18:06:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-07-09 11:10:51 -0400
commit701fac823e24676ea42451c6597f96d81d9b6aba (patch)
tree3eb175f82590b8bf4330cd050977c371f2586244 /arch/arm/mach-ep93xx/include
parent02239f0a4264608686cc0015d906c7b2dead89df (diff)
[ARM] 5578/1: ep93xx: add ep93xx-keypad clock
Add clkdev support for the ep93xx_keypad driver. A matrix keypad driver for the ep93xx just got merged via the input subsystem group. For this driver to work the keypad clock needs to be added to the ep93xx clkdev support. In order to accomplish this the following changes are implemented: 1) Move the EP93XX_EXT_*_RATE defines to mach/include/hardware.h. 2) Add EP93XX_KEYTCHCLK_DIV{4/16} for the keypad driver. 3) Add support for programmable clocks (set_rate() callback). 4) Add clk_keypad for the keypad driver. 5) tab indent the clk_lookup table for easier reading. 6) Add the set_rate() callback to program the keypad clock. This callback is generalized since the ADC clock (touchscreen) can use the same callback. 7) Use the ep93xx_syscon_swlocked_write() core function for updating the software locked register. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ep93xx/include')
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 2866297310b7..587c07bdec5b 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -12,4 +12,18 @@
12 12
13#include "ts72xx.h" 13#include "ts72xx.h"
14 14
15/*
16 * The EP93xx has two external crystal oscillators. To generate the
17 * required high-frequency clocks, the processor uses two phase-locked-
18 * loops (PLLs) to multiply the incoming external clock signal to much
19 * higher frequencies that are then divided down by programmable dividers
20 * to produce the needed clocks. The PLLs operate independently of one
21 * another.
22 */
23#define EP93XX_EXT_CLK_RATE 14745600
24#define EP93XX_EXT_RTC_RATE 32768
25
26#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)
27#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)
28
15#endif 29#endif