ARM: 6124/1: ep93xx: SPI driver platform support code

This patch adds platform side support code for the EP93xx SPI
driver. This includes clock, resources and muxing. There is a new
function: ep93xx_register_spi() which can be used by board support
code to register new SPI devices for the board.

This patch depends on patch
  5998/1 ep93xx: added chip revision reading function

Cc: Ryan Mallon <ryan@bluewatersys.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Martin Guy <martinwguy@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 5f80092b6ace..e29bdef9b2e2 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -96,6 +96,10 @@ static struct clk clk_keypad = {
         .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
         .set_rate       = set_keytchclk_rate,
 };
+static struct clk clk_spi = {
+        .parent         = &clk_xtali,
+        .rate           = EP93XX_EXT_CLK_RATE,
+};
 static struct clk clk_pwm = {
         .parent         = &clk_xtali,
         .rate           = EP93XX_EXT_CLK_RATE,
@@ -186,6 +190,7 @@ static struct clk_lookup clocks[] = {
         INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
         INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
         INIT_CK("ep93xx-fb",            NULL,           &clk_video),
+        INIT_CK("ep93xx-spi.0",         NULL,           &clk_spi),
         INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
         INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
         INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
@@ -473,6 +478,14 @@ static int __init ep93xx_clock_init(void)
         /* Initialize the pll2 derived clocks */
         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
+        /*
+         * EP93xx SSP clock rate was doubled in version E2. For more information
+         * see:
+         *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+         */
+        if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
+                clk_spi.rate /= 2;
+
         pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
         pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",