diff options
| author | Hartley Sweeten <hartleys@visionengravers.com> | 2009-05-28 15:07:03 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-05-29 15:16:31 -0400 |
| commit | 4070243250dd06a96d874b0be3cb3a39ef23597c (patch) | |
| tree | 2f0aa74a7947fdbad842a76222a9f8255a2b5e9d /arch/arm/mach-ep93xx/clock.c | |
| parent | 68ee3d83b238fa97e12775963f2b526c5dc74823 (diff) | |
[ARM] 5528/1: ep93xx: add defines for dma clock magic numbers
Update the dma clocks so that the magic numbers are named.
All the dma clocks have an enable bit to turn them on/off as
needed. Currently these bits are in the code as "magic"
numbers. This changes all of them to named defines to
improve code readability.
Also, the EP93XX_SYSCON_CLOCK_CONTROL register is improperly
named. In the EP93xx User's Guide this register is called
PwrCnt (Power Control). All of the uses of this register
are associated with the clock support so this patch also
modifies the names to match the User's Guide.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ep93xx/clock.c')
| -rw-r--r-- | arch/arm/mach-ep93xx/clock.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 29f36b458a0f..209a465bd679 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
| @@ -37,58 +37,58 @@ static struct clk clk_h; | |||
| 37 | static struct clk clk_p; | 37 | static struct clk clk_p; |
| 38 | static struct clk clk_pll2; | 38 | static struct clk clk_pll2; |
| 39 | static struct clk clk_usb_host = { | 39 | static struct clk clk_usb_host = { |
| 40 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 40 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 41 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, | 41 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | /* DMA Clocks */ | 44 | /* DMA Clocks */ |
| 45 | static struct clk clk_m2p0 = { | 45 | static struct clk clk_m2p0 = { |
| 46 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 46 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 47 | .enable_mask = 0x00020000, | 47 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, |
| 48 | }; | 48 | }; |
| 49 | static struct clk clk_m2p1 = { | 49 | static struct clk clk_m2p1 = { |
| 50 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 50 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 51 | .enable_mask = 0x00010000, | 51 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, |
| 52 | }; | 52 | }; |
| 53 | static struct clk clk_m2p2 = { | 53 | static struct clk clk_m2p2 = { |
| 54 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 54 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 55 | .enable_mask = 0x00080000, | 55 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, |
| 56 | }; | 56 | }; |
| 57 | static struct clk clk_m2p3 = { | 57 | static struct clk clk_m2p3 = { |
| 58 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 58 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 59 | .enable_mask = 0x00040000, | 59 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, |
| 60 | }; | 60 | }; |
| 61 | static struct clk clk_m2p4 = { | 61 | static struct clk clk_m2p4 = { |
| 62 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 62 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 63 | .enable_mask = 0x00200000, | 63 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, |
| 64 | }; | 64 | }; |
| 65 | static struct clk clk_m2p5 = { | 65 | static struct clk clk_m2p5 = { |
| 66 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 66 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 67 | .enable_mask = 0x00100000, | 67 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, |
| 68 | }; | 68 | }; |
| 69 | static struct clk clk_m2p6 = { | 69 | static struct clk clk_m2p6 = { |
| 70 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 70 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 71 | .enable_mask = 0x00800000, | 71 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, |
| 72 | }; | 72 | }; |
| 73 | static struct clk clk_m2p7 = { | 73 | static struct clk clk_m2p7 = { |
| 74 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 74 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 75 | .enable_mask = 0x00400000, | 75 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, |
| 76 | }; | 76 | }; |
| 77 | static struct clk clk_m2p8 = { | 77 | static struct clk clk_m2p8 = { |
| 78 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 78 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 79 | .enable_mask = 0x02000000, | 79 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, |
| 80 | }; | 80 | }; |
| 81 | static struct clk clk_m2p9 = { | 81 | static struct clk clk_m2p9 = { |
| 82 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 82 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 83 | .enable_mask = 0x01000000, | 83 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, |
| 84 | }; | 84 | }; |
| 85 | static struct clk clk_m2m0 = { | 85 | static struct clk clk_m2m0 = { |
| 86 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 86 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 87 | .enable_mask = 0x04000000, | 87 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, |
| 88 | }; | 88 | }; |
| 89 | static struct clk clk_m2m1 = { | 89 | static struct clk clk_m2m1 = { |
| 90 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 90 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 91 | .enable_mask = 0x08000000, | 91 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, |
| 92 | }; | 92 | }; |
| 93 | 93 | ||
| 94 | #define INIT_CK(dev,con,ck) \ | 94 | #define INIT_CK(dev,con,ck) \ |