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authorRusty Russell <rusty@rustcorp.com.au>2008-12-31 07:35:57 -0500
committerRusty Russell <rusty@rustcorp.com.au>2008-12-31 07:35:57 -0500
commit2ca1a615835d9f4990f42102ab1f2ef434e7e89c (patch)
tree726cf3d5f29a6c66c44e4bd68e7ebed2fd83d059 /arch/arm/mach-ep93xx/clock.c
parente12f0102ac81d660c9f801d0a0e10ccf4537a9de (diff)
parent6a94cb73064c952255336cc57731904174b2c58f (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: arch/x86/kernel/io_apic.c
Diffstat (limited to 'arch/arm/mach-ep93xx/clock.c')
-rw-r--r--arch/arm/mach-ep93xx/clock.c68
1 files changed, 23 insertions, 45 deletions
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 8c9f2491dccc..96049283a10a 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -16,11 +16,12 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/string.h> 17#include <linux/string.h>
18#include <linux/io.h> 18#include <linux/io.h>
19
20#include <asm/clkdev.h>
19#include <asm/div64.h> 21#include <asm/div64.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
22struct clk { 24struct clk {
23 char *name;
24 unsigned long rate; 25 unsigned long rate;
25 int users; 26 int users;
26 u32 enable_reg; 27 u32 enable_reg;
@@ -28,53 +29,33 @@ struct clk {
28}; 29};
29 30
30static struct clk clk_uart = { 31static struct clk clk_uart = {
31 .name = "UARTCLK",
32 .rate = 14745600, 32 .rate = 14745600,
33}; 33};
34static struct clk clk_pll1 = { 34static struct clk clk_pll1;
35 .name = "pll1", 35static struct clk clk_f;
36}; 36static struct clk clk_h;
37static struct clk clk_f = { 37static struct clk clk_p;
38 .name = "fclk", 38static struct clk clk_pll2;
39};
40static struct clk clk_h = {
41 .name = "hclk",
42};
43static struct clk clk_p = {
44 .name = "pclk",
45};
46static struct clk clk_pll2 = {
47 .name = "pll2",
48};
49static struct clk clk_usb_host = { 39static struct clk clk_usb_host = {
50 .name = "usb_host",
51 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 40 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
52 .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, 41 .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN,
53}; 42};
54 43
55 44#define INIT_CK(dev,con,ck) \
56static struct clk *clocks[] = { 45 { .dev_id = dev, .con_id = con, .clk = ck }
57 &clk_uart, 46
58 &clk_pll1, 47static struct clk_lookup clocks[] = {
59 &clk_f, 48 INIT_CK("apb:uart1", NULL, &clk_uart),
60 &clk_h, 49 INIT_CK("apb:uart2", NULL, &clk_uart),
61 &clk_p, 50 INIT_CK("apb:uart3", NULL, &clk_uart),
62 &clk_pll2, 51 INIT_CK(NULL, "pll1", &clk_pll1),
63 &clk_usb_host, 52 INIT_CK(NULL, "fclk", &clk_f),
53 INIT_CK(NULL, "hclk", &clk_h),
54 INIT_CK(NULL, "pclk", &clk_p),
55 INIT_CK(NULL, "pll2", &clk_pll2),
56 INIT_CK(NULL, "usb_host", &clk_usb_host),
64}; 57};
65 58
66struct clk *clk_get(struct device *dev, const char *id)
67{
68 int i;
69
70 for (i = 0; i < ARRAY_SIZE(clocks); i++) {
71 if (!strcmp(clocks[i]->name, id))
72 return clocks[i];
73 }
74
75 return ERR_PTR(-ENOENT);
76}
77EXPORT_SYMBOL(clk_get);
78 59
79int clk_enable(struct clk *clk) 60int clk_enable(struct clk *clk)
80{ 61{
@@ -106,12 +87,6 @@ unsigned long clk_get_rate(struct clk *clk)
106} 87}
107EXPORT_SYMBOL(clk_get_rate); 88EXPORT_SYMBOL(clk_get_rate);
108 89
109void clk_put(struct clk *clk)
110{
111}
112EXPORT_SYMBOL(clk_put);
113
114
115 90
116static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 91static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
117static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 92static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
@@ -138,6 +113,7 @@ static unsigned long calc_pll_rate(u32 config_word)
138static int __init ep93xx_clock_init(void) 113static int __init ep93xx_clock_init(void)
139{ 114{
140 u32 value; 115 u32 value;
116 int i;
141 117
142 value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); 118 value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
143 if (!(value & 0x00800000)) { /* PLL1 bypassed? */ 119 if (!(value & 0x00800000)) { /* PLL1 bypassed? */
@@ -165,6 +141,8 @@ static int __init ep93xx_clock_init(void)
165 clk_f.rate / 1000000, clk_h.rate / 1000000, 141 clk_f.rate / 1000000, clk_h.rate / 1000000,
166 clk_p.rate / 1000000); 142 clk_p.rate / 1000000);
167 143
144 for (i = 0; i < ARRAY_SIZE(clocks); i++)
145 clkdev_add(&clocks[i]);
168 return 0; 146 return 0;
169} 147}
170arch_initcall(ep93xx_clock_init); 148arch_initcall(ep93xx_clock_init);