[ARM] 5577/2: ep93xx: syscon locked register functions

Add core functions to handle writes to the ep93xx software locked
registers.

There are a number of registers in the EP93xx System Controller
that require a write to the software lock register before they
can be updated. This patch adds a number of exported functions
to the ep93xx core that handle this access.

The software locked clock divider registers, VidClkDiv, MIRClkDiv,
I2SClkDiv and KeyTchClkDiv would typically involve writing a
specific value to the register. To support this the
ep93xx_syscon_swlocked_write() function is provided.

For the DeviceCfg register it's more typical to only need to
set or clear a single bit. A generic ep93xx_devcfg_set_clear()
function is provided to handle both operations. Two inline
functions, ep93xx_devcfg_set_bits() and ep93xx_devcfg_clear_bits()
are also provided to improve code readability.

In addition, the remaining bits in the System Controller Device
Config Register have been documented and the previously defined
names shortened.

All code paths that use this functionality have been updated
except for arch/arm/kernel/crunch.c. That code is in a context
switch path, which is not reentrant, so it is safe against itself.

Cc: Lennert Buytenhek <buytenh@wantstofly.org>
Cc: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 14 insertions, 10 deletions

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6c4c1633ed12..c7642acfd022 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -50,20 +50,20 @@ static unsigned long get_uart_rate(struct clk *clk);
 
 static struct clk clk_uart1 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart2 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart3 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_pll1;
@@ -160,9 +160,11 @@ int clk_enable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value |= clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value | clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 
         return 0;
@@ -175,9 +177,11 @@ void clk_disable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value &= ~clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 }
 EXPORT_SYMBOL(clk_disable);