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authorSaeed Bishara <saeed@marvell.com>2009-08-06 08:12:43 -0400
committerNicolas Pitre <nico@fluxnic.net>2009-11-27 15:43:06 -0500
commitedabd38e1a017e922e3e3b485ee3ddb4df433aa4 (patch)
treec79cef3e59f62014c12ff1203e84b0bac5610a55 /arch/arm/mach-dove
parent8d27b2f7988b652dbabf79291a3e2550c06e1af5 (diff)
ARM: add base support for Marvell Dove SoC
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-dove')
-rw-r--r--arch/arm/mach-dove/Kconfig14
-rw-r--r--arch/arm/mach-dove/Makefile3
-rw-r--r--arch/arm/mach-dove/Makefile.boot3
-rw-r--r--arch/arm/mach-dove/addr-map.c149
-rw-r--r--arch/arm/mach-dove/common.c777
-rw-r--r--arch/arm/mach-dove/common.h40
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c102
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h58
-rw-r--r--arch/arm/mach-dove/include/mach/debug-macro.S20
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h180
-rw-r--r--arch/arm/mach-dove/include/mach/entry-macro.S39
-rw-r--r--arch/arm/mach-dove/include/mach/gpio.h49
-rw-r--r--arch/arm/mach-dove/include/mach/hardware.h26
-rw-r--r--arch/arm/mach-dove/include/mach/io.h20
-rw-r--r--arch/arm/mach-dove/include/mach/irqs.h101
-rw-r--r--arch/arm/mach-dove/include/mach/memory.h10
-rw-r--r--arch/arm/mach-dove/include/mach/pm.h54
-rw-r--r--arch/arm/mach-dove/include/mach/system.h36
-rw-r--r--arch/arm/mach-dove/include/mach/timex.h9
-rw-r--r--arch/arm/mach-dove/include/mach/uncompress.h37
-rw-r--r--arch/arm/mach-dove/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-dove/irq.c133
-rw-r--r--arch/arm/mach-dove/pcie.c238
23 files changed, 2103 insertions, 0 deletions
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
new file mode 100644
index 000000000000..3b9a32ace909
--- /dev/null
+++ b/arch/arm/mach-dove/Kconfig
@@ -0,0 +1,14 @@
1if ARCH_DOVE
2
3menu "Marvell Dove Implementations"
4
5config MACH_DOVE_DB
6 bool "Marvell DB-MV88AP510 Development Board"
7 select I2C_BOARDINFO
8 help
9 Say 'Y' here if you want your kernel to support the
10 Marvell DB-MV88AP510 Development Board.
11
12endmenu
13
14endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
new file mode 100644
index 000000000000..7ab3be53f642
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile
@@ -0,0 +1,3 @@
1obj-y += common.o addr-map.o irq.o pcie.o
2
3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
new file mode 100644
index 000000000000..00be4fc26dd7
--- /dev/null
+++ b/arch/arm/mach-dove/addr-map.c
@@ -0,0 +1,149 @@
1/*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include "common.h"
18
19/*
20 * Generic Address Decode Windows bit settings
21 */
22#define TARGET_DDR 0x0
23#define TARGET_BOOTROM 0x1
24#define TARGET_CESA 0x3
25#define TARGET_PCIE0 0x4
26#define TARGET_PCIE1 0x8
27#define TARGET_SCRATCHPAD 0xd
28
29#define ATTR_CESA 0x01
30#define ATTR_BOOTROM 0xfd
31#define ATTR_DEV_SPI0_ROM 0xfe
32#define ATTR_DEV_SPI1_ROM 0xfb
33#define ATTR_PCIE_IO 0xe0
34#define ATTR_PCIE_MEM 0xe8
35#define ATTR_SCRATCHPAD 0x0
36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45struct mbus_dram_target_info dove_mbus_dram_info;
46
47static inline void __iomem *ddr_map_sc(int i)
48{
49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
50}
51
52static int cpu_win_can_remap(int win)
53{
54 if (win < 4)
55 return 1;
56
57 return 0;
58}
59
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76}
77
78void __init dove_setup_cpu_mbus(void)
79{
80 int i;
81 int cs;
82
83 /*
84 * First, disable and clear windows.
85 */
86 for (i = 0; i < 8; i++) {
87 writel(0, WIN_BASE(i));
88 writel(0, WIN_CTRL(i));
89 if (cpu_win_can_remap(i)) {
90 writel(0, WIN_REMAP_LO(i));
91 writel(0, WIN_REMAP_HI(i));
92 }
93 }
94
95 /*
96 * Setup windows for PCIe IO+MEM space.
97 */
98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
107 /*
108 * Setup window for CESA engine.
109 */
110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
111 TARGET_CESA, ATTR_CESA, -1);
112
113 /*
114 * Setup the Window to the BootROM for Standby and Sleep Resume
115 */
116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
117 TARGET_BOOTROM, ATTR_BOOTROM, -1);
118
119 /*
120 * Setup the Window to the PMU Scratch Pad space
121 */
122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
124
125 /*
126 * Setup MBUS dram target info.
127 */
128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
129
130 for (i = 0, cs = 0; i < 2; i++) {
131 u32 map = readl(ddr_map_sc(i));
132
133 /*
134 * Chip select enabled?
135 */
136 if (map & 1) {
137 struct mbus_dram_window *w;
138
139 w = &dove_mbus_dram_info.cs[cs++];
140 w->cs_index = i;
141 w->mbus_attr = 0; /* CS address decoding done inside */
142 /* the DDR controller, no need to */
143 /* provide attributes */
144 w->base = map & 0xff800000;
145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
146 }
147 }
148 dove_mbus_dram_info.num_cs = cs;
149}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
new file mode 100644
index 000000000000..a20cf099cd97
--- /dev/null
+++ b/arch/arm/mach-dove/common.c
@@ -0,0 +1,777 @@
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/serial_8250.h>
17#include <linux/clk.h>
18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h>
23#include <linux/gpio.h>
24#include <asm/page.h>
25#include <asm/setup.h>
26#include <asm/timex.h>
27#include <asm/mach/map.h>
28#include <asm/mach/time.h>
29#include <asm/mach/pci.h>
30#include <mach/dove.h>
31#include <mach/bridge-regs.h>
32#include <asm/mach/arch.h>
33#include <linux/irq.h>
34#include <plat/mv_xor.h>
35#include <plat/ehci-orion.h>
36#include <plat/time.h>
37#include "common.h"
38
39/*****************************************************************************
40 * I/O Address Mapping
41 ****************************************************************************/
42static struct map_desc dove_io_desc[] __initdata = {
43 {
44 .virtual = DOVE_SB_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
46 .length = DOVE_SB_REGS_SIZE,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = DOVE_NB_REGS_VIRT_BASE,
50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
51 .length = DOVE_NB_REGS_SIZE,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
55 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
56 .length = DOVE_PCIE0_IO_SIZE,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
60 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
61 .length = DOVE_PCIE1_IO_SIZE,
62 .type = MT_DEVICE,
63 },
64};
65
66void __init dove_map_io(void)
67{
68 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
69}
70
71/*****************************************************************************
72 * EHCI
73 ****************************************************************************/
74static struct orion_ehci_data dove_ehci_data = {
75 .dram = &dove_mbus_dram_info,
76 .phy_version = EHCI_PHY_NA,
77};
78
79static u64 ehci_dmamask = DMA_BIT_MASK(32);
80
81/*****************************************************************************
82 * EHCI0
83 ****************************************************************************/
84static struct resource dove_ehci0_resources[] = {
85 {
86 .start = DOVE_USB0_PHYS_BASE,
87 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = IRQ_DOVE_USB0,
91 .end = IRQ_DOVE_USB0,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device dove_ehci0 = {
97 .name = "orion-ehci",
98 .id = 0,
99 .dev = {
100 .dma_mask = &ehci_dmamask,
101 .coherent_dma_mask = DMA_BIT_MASK(32),
102 .platform_data = &dove_ehci_data,
103 },
104 .resource = dove_ehci0_resources,
105 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
106};
107
108void __init dove_ehci0_init(void)
109{
110 platform_device_register(&dove_ehci0);
111}
112
113/*****************************************************************************
114 * EHCI1
115 ****************************************************************************/
116static struct resource dove_ehci1_resources[] = {
117 {
118 .start = DOVE_USB1_PHYS_BASE,
119 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
120 .flags = IORESOURCE_MEM,
121 }, {
122 .start = IRQ_DOVE_USB1,
123 .end = IRQ_DOVE_USB1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct platform_device dove_ehci1 = {
129 .name = "orion-ehci",
130 .id = 1,
131 .dev = {
132 .dma_mask = &ehci_dmamask,
133 .coherent_dma_mask = DMA_BIT_MASK(32),
134 .platform_data = &dove_ehci_data,
135 },
136 .resource = dove_ehci1_resources,
137 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
138};
139
140void __init dove_ehci1_init(void)
141{
142 platform_device_register(&dove_ehci1);
143}
144
145/*****************************************************************************
146 * GE00
147 ****************************************************************************/
148struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
149 .t_clk = 0,
150 .dram = &dove_mbus_dram_info,
151};
152
153static struct resource dove_ge00_shared_resources[] = {
154 {
155 .name = "ge00 base",
156 .start = DOVE_GE00_PHYS_BASE + 0x2000,
157 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162static struct platform_device dove_ge00_shared = {
163 .name = MV643XX_ETH_SHARED_NAME,
164 .id = 0,
165 .dev = {
166 .platform_data = &dove_ge00_shared_data,
167 },
168 .num_resources = 1,
169 .resource = dove_ge00_shared_resources,
170};
171
172static struct resource dove_ge00_resources[] = {
173 {
174 .name = "ge00 irq",
175 .start = IRQ_DOVE_GE00_SUM,
176 .end = IRQ_DOVE_GE00_SUM,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device dove_ge00 = {
182 .name = MV643XX_ETH_NAME,
183 .id = 0,
184 .num_resources = 1,
185 .resource = dove_ge00_resources,
186 .dev = {
187 .coherent_dma_mask = 0xffffffff,
188 },
189};
190
191void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
192{
193 eth_data->shared = &dove_ge00_shared;
194 dove_ge00.dev.platform_data = eth_data;
195
196 platform_device_register(&dove_ge00_shared);
197 platform_device_register(&dove_ge00);
198}
199
200/*****************************************************************************
201 * SoC RTC
202 ****************************************************************************/
203static struct resource dove_rtc_resource[] = {
204 {
205 .start = DOVE_RTC_PHYS_BASE,
206 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
207 .flags = IORESOURCE_MEM,
208 }, {
209 .start = IRQ_DOVE_RTC,
210 .flags = IORESOURCE_IRQ,
211 }
212};
213
214void __init dove_rtc_init(void)
215{
216 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
217}
218
219/*****************************************************************************
220 * SATA
221 ****************************************************************************/
222static struct resource dove_sata_resources[] = {
223 {
224 .name = "sata base",
225 .start = DOVE_SATA_PHYS_BASE,
226 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
227 .flags = IORESOURCE_MEM,
228 }, {
229 .name = "sata irq",
230 .start = IRQ_DOVE_SATA,
231 .end = IRQ_DOVE_SATA,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct platform_device dove_sata = {
237 .name = "sata_mv",
238 .id = 0,
239 .dev = {
240 .coherent_dma_mask = DMA_BIT_MASK(32),
241 },
242 .num_resources = ARRAY_SIZE(dove_sata_resources),
243 .resource = dove_sata_resources,
244};
245
246void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
247{
248 sata_data->dram = &dove_mbus_dram_info;
249 dove_sata.dev.platform_data = sata_data;
250 platform_device_register(&dove_sata);
251}
252
253/*****************************************************************************
254 * UART0
255 ****************************************************************************/
256static struct plat_serial8250_port dove_uart0_data[] = {
257 {
258 .mapbase = DOVE_UART0_PHYS_BASE,
259 .membase = (char *)DOVE_UART0_VIRT_BASE,
260 .irq = IRQ_DOVE_UART_0,
261 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
262 .iotype = UPIO_MEM,
263 .regshift = 2,
264 .uartclk = 0,
265 }, {
266 },
267};
268
269static struct resource dove_uart0_resources[] = {
270 {
271 .start = DOVE_UART0_PHYS_BASE,
272 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
273 .flags = IORESOURCE_MEM,
274 }, {
275 .start = IRQ_DOVE_UART_0,
276 .end = IRQ_DOVE_UART_0,
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct platform_device dove_uart0 = {
282 .name = "serial8250",
283 .id = 0,
284 .dev = {
285 .platform_data = dove_uart0_data,
286 },
287 .resource = dove_uart0_resources,
288 .num_resources = ARRAY_SIZE(dove_uart0_resources),
289};
290
291void __init dove_uart0_init(void)
292{
293 platform_device_register(&dove_uart0);
294}
295
296/*****************************************************************************
297 * UART1
298 ****************************************************************************/
299static struct plat_serial8250_port dove_uart1_data[] = {
300 {
301 .mapbase = DOVE_UART1_PHYS_BASE,
302 .membase = (char *)DOVE_UART1_VIRT_BASE,
303 .irq = IRQ_DOVE_UART_1,
304 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
305 .iotype = UPIO_MEM,
306 .regshift = 2,
307 .uartclk = 0,
308 }, {
309 },
310};
311
312static struct resource dove_uart1_resources[] = {
313 {
314 .start = DOVE_UART1_PHYS_BASE,
315 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
316 .flags = IORESOURCE_MEM,
317 }, {
318 .start = IRQ_DOVE_UART_1,
319 .end = IRQ_DOVE_UART_1,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct platform_device dove_uart1 = {
325 .name = "serial8250",
326 .id = 1,
327 .dev = {
328 .platform_data = dove_uart1_data,
329 },
330 .resource = dove_uart1_resources,
331 .num_resources = ARRAY_SIZE(dove_uart1_resources),
332};
333
334void __init dove_uart1_init(void)
335{
336 platform_device_register(&dove_uart1);
337}
338
339/*****************************************************************************
340 * UART2
341 ****************************************************************************/
342static struct plat_serial8250_port dove_uart2_data[] = {
343 {
344 .mapbase = DOVE_UART2_PHYS_BASE,
345 .membase = (char *)DOVE_UART2_VIRT_BASE,
346 .irq = IRQ_DOVE_UART_2,
347 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
348 .iotype = UPIO_MEM,
349 .regshift = 2,
350 .uartclk = 0,
351 }, {
352 },
353};
354
355static struct resource dove_uart2_resources[] = {
356 {
357 .start = DOVE_UART2_PHYS_BASE,
358 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
359 .flags = IORESOURCE_MEM,
360 }, {
361 .start = IRQ_DOVE_UART_2,
362 .end = IRQ_DOVE_UART_2,
363 .flags = IORESOURCE_IRQ,
364 },
365};
366
367static struct platform_device dove_uart2 = {
368 .name = "serial8250",
369 .id = 2,
370 .dev = {
371 .platform_data = dove_uart2_data,
372 },
373 .resource = dove_uart2_resources,
374 .num_resources = ARRAY_SIZE(dove_uart2_resources),
375};
376
377void __init dove_uart2_init(void)
378{
379 platform_device_register(&dove_uart2);
380}
381
382/*****************************************************************************
383 * UART3
384 ****************************************************************************/
385static struct plat_serial8250_port dove_uart3_data[] = {
386 {
387 .mapbase = DOVE_UART3_PHYS_BASE,
388 .membase = (char *)DOVE_UART3_VIRT_BASE,
389 .irq = IRQ_DOVE_UART_3,
390 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
391 .iotype = UPIO_MEM,
392 .regshift = 2,
393 .uartclk = 0,
394 }, {
395 },
396};
397
398static struct resource dove_uart3_resources[] = {
399 {
400 .start = DOVE_UART3_PHYS_BASE,
401 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
402 .flags = IORESOURCE_MEM,
403 }, {
404 .start = IRQ_DOVE_UART_3,
405 .end = IRQ_DOVE_UART_3,
406 .flags = IORESOURCE_IRQ,
407 },
408};
409
410static struct platform_device dove_uart3 = {
411 .name = "serial8250",
412 .id = 3,
413 .dev = {
414 .platform_data = dove_uart3_data,
415 },
416 .resource = dove_uart3_resources,
417 .num_resources = ARRAY_SIZE(dove_uart3_resources),
418};
419
420void __init dove_uart3_init(void)
421{
422 platform_device_register(&dove_uart3);
423}
424
425/*****************************************************************************
426 * SPI0
427 ****************************************************************************/
428static struct orion_spi_info dove_spi0_data = {
429 .tclk = 0,
430};
431
432static struct resource dove_spi0_resources[] = {
433 {
434 .start = DOVE_SPI0_PHYS_BASE,
435 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
436 .flags = IORESOURCE_MEM,
437 }, {
438 .start = IRQ_DOVE_SPI0,
439 .end = IRQ_DOVE_SPI0,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device dove_spi0 = {
445 .name = "orion_spi",
446 .id = 0,
447 .resource = dove_spi0_resources,
448 .dev = {
449 .platform_data = &dove_spi0_data,
450 },
451 .num_resources = ARRAY_SIZE(dove_spi0_resources),
452};
453
454void __init dove_spi0_init(void)
455{
456 platform_device_register(&dove_spi0);
457}
458
459/*****************************************************************************
460 * SPI1
461 ****************************************************************************/
462static struct orion_spi_info dove_spi1_data = {
463 .tclk = 0,
464};
465
466static struct resource dove_spi1_resources[] = {
467 {
468 .start = DOVE_SPI1_PHYS_BASE,
469 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
470 .flags = IORESOURCE_MEM,
471 }, {
472 .start = IRQ_DOVE_SPI1,
473 .end = IRQ_DOVE_SPI1,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct platform_device dove_spi1 = {
479 .name = "orion_spi",
480 .id = 1,
481 .resource = dove_spi1_resources,
482 .dev = {
483 .platform_data = &dove_spi1_data,
484 },
485 .num_resources = ARRAY_SIZE(dove_spi1_resources),
486};
487
488void __init dove_spi1_init(void)
489{
490 platform_device_register(&dove_spi1);
491}
492
493/*****************************************************************************
494 * I2C
495 ****************************************************************************/
496static struct mv64xxx_i2c_pdata dove_i2c_data = {
497 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
498 .freq_n = 3,
499 .timeout = 1000, /* Default timeout of 1 second */
500};
501
502static struct resource dove_i2c_resources[] = {
503 {
504 .name = "i2c base",
505 .start = DOVE_I2C_PHYS_BASE,
506 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
507 .flags = IORESOURCE_MEM,
508 }, {
509 .name = "i2c irq",
510 .start = IRQ_DOVE_I2C,
511 .end = IRQ_DOVE_I2C,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516static struct platform_device dove_i2c = {
517 .name = MV64XXX_I2C_CTLR_NAME,
518 .id = 0,
519 .num_resources = ARRAY_SIZE(dove_i2c_resources),
520 .resource = dove_i2c_resources,
521 .dev = {
522 .platform_data = &dove_i2c_data,
523 },
524};
525
526void __init dove_i2c_init(void)
527{
528 platform_device_register(&dove_i2c);
529}
530
531/*****************************************************************************
532 * Time handling
533 ****************************************************************************/
534static int get_tclk(void)
535{
536 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
537 return 166666667;
538}
539
540static void dove_timer_init(void)
541{
542 orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
543}
544
545struct sys_timer dove_timer = {
546 .init = dove_timer_init,
547};
548
549/*****************************************************************************
550 * XOR
551 ****************************************************************************/
552static struct mv_xor_platform_shared_data dove_xor_shared_data = {
553 .dram = &dove_mbus_dram_info,
554};
555
556/*****************************************************************************
557 * XOR 0
558 ****************************************************************************/
559static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
560
561static struct resource dove_xor0_shared_resources[] = {
562 {
563 .name = "xor 0 low",
564 .start = DOVE_XOR0_PHYS_BASE,
565 .end = DOVE_XOR0_PHYS_BASE + 0xff,
566 .flags = IORESOURCE_MEM,
567 }, {
568 .name = "xor 0 high",
569 .start = DOVE_XOR0_HIGH_PHYS_BASE,
570 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
571 .flags = IORESOURCE_MEM,
572 },
573};
574
575static struct platform_device dove_xor0_shared = {
576 .name = MV_XOR_SHARED_NAME,
577 .id = 0,
578 .dev = {
579 .platform_data = &dove_xor_shared_data,
580 },
581 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
582 .resource = dove_xor0_shared_resources,
583};
584
585static struct resource dove_xor00_resources[] = {
586 [0] = {
587 .start = IRQ_DOVE_XOR_00,
588 .end = IRQ_DOVE_XOR_00,
589 .flags = IORESOURCE_IRQ,
590 },
591};
592
593static struct mv_xor_platform_data dove_xor00_data = {
594 .shared = &dove_xor0_shared,
595 .hw_id = 0,
596 .pool_size = PAGE_SIZE,
597};
598
599static struct platform_device dove_xor00_channel = {
600 .name = MV_XOR_NAME,
601 .id = 0,
602 .num_resources = ARRAY_SIZE(dove_xor00_resources),
603 .resource = dove_xor00_resources,
604 .dev = {
605 .dma_mask = &dove_xor0_dmamask,
606 .coherent_dma_mask = DMA_BIT_MASK(64),
607 .platform_data = (void *)&dove_xor00_data,
608 },
609};
610
611static struct resource dove_xor01_resources[] = {
612 [0] = {
613 .start = IRQ_DOVE_XOR_01,
614 .end = IRQ_DOVE_XOR_01,
615 .flags = IORESOURCE_IRQ,
616 },
617};
618
619static struct mv_xor_platform_data dove_xor01_data = {
620 .shared = &dove_xor0_shared,
621 .hw_id = 1,
622 .pool_size = PAGE_SIZE,
623};
624
625static struct platform_device dove_xor01_channel = {
626 .name = MV_XOR_NAME,
627 .id = 1,
628 .num_resources = ARRAY_SIZE(dove_xor01_resources),
629 .resource = dove_xor01_resources,
630 .dev = {
631 .dma_mask = &dove_xor0_dmamask,
632 .coherent_dma_mask = DMA_BIT_MASK(64),
633 .platform_data = (void *)&dove_xor01_data,
634 },
635};
636
637void __init dove_xor0_init(void)
638{
639 platform_device_register(&dove_xor0_shared);
640
641 /*
642 * two engines can't do memset simultaneously, this limitation
643 * satisfied by removing memset support from one of the engines.
644 */
645 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
646 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
647 platform_device_register(&dove_xor00_channel);
648
649 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
650 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
651 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
652 platform_device_register(&dove_xor01_channel);
653}
654
655/*****************************************************************************
656 * XOR 1
657 ****************************************************************************/
658static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
659
660static struct resource dove_xor1_shared_resources[] = {
661 {
662 .name = "xor 0 low",
663 .start = DOVE_XOR1_PHYS_BASE,
664 .end = DOVE_XOR1_PHYS_BASE + 0xff,
665 .flags = IORESOURCE_MEM,
666 }, {
667 .name = "xor 0 high",
668 .start = DOVE_XOR1_HIGH_PHYS_BASE,
669 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
670 .flags = IORESOURCE_MEM,
671 },
672};
673
674static struct platform_device dove_xor1_shared = {
675 .name = MV_XOR_SHARED_NAME,
676 .id = 1,
677 .dev = {
678 .platform_data = &dove_xor_shared_data,
679 },
680 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
681 .resource = dove_xor1_shared_resources,
682};
683
684static struct resource dove_xor10_resources[] = {
685 [0] = {
686 .start = IRQ_DOVE_XOR_10,
687 .end = IRQ_DOVE_XOR_10,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692static struct mv_xor_platform_data dove_xor10_data = {
693 .shared = &dove_xor1_shared,
694 .hw_id = 0,
695 .pool_size = PAGE_SIZE,
696};
697
698static struct platform_device dove_xor10_channel = {
699 .name = MV_XOR_NAME,
700 .id = 2,
701 .num_resources = ARRAY_SIZE(dove_xor10_resources),
702 .resource = dove_xor10_resources,
703 .dev = {
704 .dma_mask = &dove_xor1_dmamask,
705 .coherent_dma_mask = DMA_BIT_MASK(64),
706 .platform_data = (void *)&dove_xor10_data,
707 },
708};
709
710static struct resource dove_xor11_resources[] = {
711 [0] = {
712 .start = IRQ_DOVE_XOR_11,
713 .end = IRQ_DOVE_XOR_11,
714 .flags = IORESOURCE_IRQ,
715 },
716};
717
718static struct mv_xor_platform_data dove_xor11_data = {
719 .shared = &dove_xor1_shared,
720 .hw_id = 1,
721 .pool_size = PAGE_SIZE,
722};
723
724static struct platform_device dove_xor11_channel = {
725 .name = MV_XOR_NAME,
726 .id = 3,
727 .num_resources = ARRAY_SIZE(dove_xor11_resources),
728 .resource = dove_xor11_resources,
729 .dev = {
730 .dma_mask = &dove_xor1_dmamask,
731 .coherent_dma_mask = DMA_BIT_MASK(64),
732 .platform_data = (void *)&dove_xor11_data,
733 },
734};
735
736void __init dove_xor1_init(void)
737{
738 platform_device_register(&dove_xor1_shared);
739
740 /*
741 * two engines can't do memset simultaneously, this limitation
742 * satisfied by removing memset support from one of the engines.
743 */
744 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
745 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
746 platform_device_register(&dove_xor10_channel);
747
748 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
749 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
750 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
751 platform_device_register(&dove_xor11_channel);
752}
753
754void __init dove_init(void)
755{
756 int tclk;
757
758 tclk = get_tclk();
759
760 printk(KERN_INFO "Dove 88AP510 SoC, ");
761 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
762
763 dove_setup_cpu_mbus();
764
765 dove_ge00_shared_data.t_clk = tclk;
766 dove_uart0_data[0].uartclk = tclk;
767 dove_uart1_data[0].uartclk = tclk;
768 dove_uart2_data[0].uartclk = tclk;
769 dove_uart3_data[0].uartclk = tclk;
770 dove_spi0_data.tclk = tclk;
771 dove_spi1_data.tclk = tclk;
772
773 /* internal devices that every board has */
774 dove_rtc_init();
775 dove_xor0_init();
776 dove_xor1_init();
777}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
new file mode 100644
index 000000000000..b29e8937de4f
--- /dev/null
+++ b/arch/arm/mach-dove/common.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-dove/common.h
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_DOVE_COMMON_H
12#define __ARCH_DOVE_COMMON_H
13
14struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data;
16
17extern struct sys_timer dove_timer;
18extern struct mbus_dram_target_info dove_mbus_dram_info;
19
20/*
21 * Basic Dove init functions used early by machine-setup.
22 */
23void dove_map_io(void);
24void dove_init(void);
25void dove_init_irq(void);
26void dove_setup_cpu_mbus(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
28void dove_sata_init(struct mv_sata_platform_data *sata_data);
29void dove_pcie_init(int init_port0, int init_port1);
30void dove_ehci0_init(void);
31void dove_ehci1_init(void);
32void dove_uart0_init(void);
33void dove_uart1_init(void);
34void dove_uart2_init(void);
35void dove_uart3_init(void);
36void dove_spi0_init(void);
37void dove_spi1_init(void);
38void dove_i2c_init(void);
39
40#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
new file mode 100644
index 000000000000..f2971b745224
--- /dev/null
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -0,0 +1,102 @@
1/*
2 * arch/arm/mach-dove/dove-db-setup.c
3 *
4 * Marvell DB-MV88AP510-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/nand.h>
17#include <linux/timer.h>
18#include <linux/ata_platform.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/i2c.h>
21#include <linux/pci.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/orion_spi.h>
24#include <linux/spi/flash.h>
25#include <linux/gpio.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/dove.h>
29#include "common.h"
30
31static struct mv643xx_eth_platform_data dove_db_ge00_data = {
32 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
33};
34
35static struct mv_sata_platform_data dove_db_sata_data = {
36 .n_ports = 1,
37};
38
39/*****************************************************************************
40 * SPI Devices:
41 * SPI0: 4M Flash ST-M25P32-VMF6P
42 ****************************************************************************/
43static const struct flash_platform_data dove_db_spi_flash_data = {
44 .type = "m25p64",
45};
46
47static struct spi_board_info __initdata dove_db_spi_flash_info[] = {
48 {
49 .modalias = "m25p80",
50 .platform_data = &dove_db_spi_flash_data,
51 .irq = -1,
52 .max_speed_hz = 20000000,
53 .bus_num = 0,
54 .chip_select = 0,
55 },
56};
57
58/*****************************************************************************
59 * PCI
60 ****************************************************************************/
61static int __init dove_db_pci_init(void)
62{
63 if (machine_is_dove_db())
64 dove_pcie_init(1, 1);
65
66 return 0;
67}
68
69subsys_initcall(dove_db_pci_init);
70
71/*****************************************************************************
72 * Board Init
73 ****************************************************************************/
74static void __init dove_db_init(void)
75{
76 /*
77 * Basic Dove setup. Needs to be called early.
78 */
79 dove_init();
80
81 dove_ge00_init(&dove_db_ge00_data);
82 dove_ehci0_init();
83 dove_ehci1_init();
84 dove_sata_init(&dove_db_sata_data);
85 dove_spi0_init();
86 dove_spi1_init();
87 dove_uart0_init();
88 dove_uart1_init();
89 dove_i2c_init();
90 spi_register_board_info(dove_db_spi_flash_info,
91 ARRAY_SIZE(dove_db_spi_flash_info));
92}
93
94MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
95 .phys_io = DOVE_SB_REGS_PHYS_BASE,
96 .io_pg_offst = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
97 .boot_params = 0x00000100,
98 .init_machine = dove_db_init,
99 .map_io = dove_map_io,
100 .init_irq = dove_init_irq,
101 .timer = &dove_timer,
102MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
new file mode 100644
index 000000000000..214a4c31f069
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -0,0 +1,58 @@
1/*
2 * arch/arm/mach-dove/include/mach/bridge-regs.h
3 *
4 * Mbus-L to Mbus Bridge Registers
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/dove.h>
15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008
22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004
25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
27#define SOFT_RESET 0x00000001
28
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
30#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
31#define BRIDGE_INT_TIMER0 0x0002
32#define BRIDGE_INT_TIMER1 0x0004
33#define BRIDGE_INT_TIMER1_CLR (~0x0004)
34
35#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
36#define IRQ_CAUSE_LOW_OFF 0x0000
37#define IRQ_MASK_LOW_OFF 0x0004
38#define FIQ_MASK_LOW_OFF 0x0008
39#define ENDPOINT_MASK_LOW_OFF 0x000c
40#define IRQ_CAUSE_HIGH_OFF 0x0010
41#define IRQ_MASK_HIGH_OFF 0x0014
42#define FIQ_MASK_HIGH_OFF 0x0018
43#define ENDPOINT_MASK_HIGH_OFF 0x001c
44#define PCIE_INTERRUPT_MASK_OFF 0x0020
45
46#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
47#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
48#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
49#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
50#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
51#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
52#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
53
54#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
55
56#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
57
58#endif
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9b89ec7d3040
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-dove/include/mach/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <mach/bridge-regs.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =DOVE_SB_REGS_PHYS_BASE
15 ldrne \rx, =DOVE_SB_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
new file mode 100644
index 000000000000..f6a08397f046
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-dove/include/mach/dove.h
3 *
4 * Generic definitions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_DOVE_H
12#define __ASM_ARCH_DOVE_H
13
14#include <mach/vmalloc.h>
15
16/*
17 * Marvell Dove address maps.
18 *
19 * phys virt size
20 * c8000000 fdb00000 1M Cryptographic SRAM
21 * e0000000 @runtime 128M PCIe-0 Memory space
22 * e8000000 @runtime 128M PCIe-1 Memory space
23 * f1000000 fde00000 8M on-chip south-bridge registers
24 * f1800000 fe600000 8M on-chip north-bridge registers
25 * f2000000 fee00000 1M PCIe-0 I/O space
26 * f2100000 fef00000 1M PCIe-1 I/O space
27 */
28
29#define DOVE_CESA_PHYS_BASE 0xc8000000
30#define DOVE_CESA_VIRT_BASE 0xfdb00000
31#define DOVE_CESA_SIZE SZ_1M
32
33#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34#define DOVE_PCIE0_MEM_SIZE SZ_128M
35
36#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37#define DOVE_PCIE1_MEM_SIZE SZ_128M
38
39#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40#define DOVE_BOOTROM_SIZE SZ_128M
41
42#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
43#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000
44#define DOVE_SCRATCHPAD_SIZE SZ_1M
45
46#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
47#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
48#define DOVE_SB_REGS_SIZE SZ_8M
49
50#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
51#define DOVE_NB_REGS_VIRT_BASE 0xfe600000
52#define DOVE_NB_REGS_SIZE SZ_8M
53
54#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
55#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
56#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
57#define DOVE_PCIE0_IO_SIZE SZ_1M
58
59#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
60#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000
61#define DOVE_PCIE1_IO_BUS_BASE 0x00100000
62#define DOVE_PCIE1_IO_SIZE SZ_1M
63
64/*
65 * Dove Core Registers Map
66 */
67
68/* SPI, I2C, UART */
69#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000)
70#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000)
71#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000)
72#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100)
73#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100)
74#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200)
75#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200)
76#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300)
77#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300)
78#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600)
79#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600)
80
81/* North-South Bridge */
82#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
83
84/* Cryptographic Engine */
85#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
86
87/* PCIe 0 */
88#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000)
89
90/* USB */
91#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000)
92#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000)
93
94/* XOR 0 Engine */
95#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800)
96#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800)
97#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
98#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
99
100/* XOR 1 Engine */
101#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900)
102#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900)
103#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
104#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
105
106/* Gigabit Ethernet */
107#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000)
108
109/* PCIe 1 */
110#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000)
111
112/* CAFE */
113#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000)
114#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000)
115#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000)
116#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
117
118/* SATA */
119#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
120
121/* I2S/SPDIF */
122#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
123#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
124
125/* NAND Flash Controller */
126#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
127
128/* MPP, GPIO, Reset Sampling */
129#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
130#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
133#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
134#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
135#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
136#define DOVE_NAND_GPIO_EN (1 << 0)
137#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
138
139
140/* Power Management */
141#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
142
143/* Real Time Clock */
144#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
145
146/* AC97 */
147#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
148#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
149
150/* Peripheral DMA */
151#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
152#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
153
154#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
155#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
156#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
157#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
158#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
159#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
160#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000)
161#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
162#define DOVE_SSP_ON_AU1 (1 << 0)
163#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
164#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
165/* Memory Controller */
166#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000)
167
168/* LCD Controller */
169#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
170#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000)
171#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
172#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
173
174/* Graphic Engine */
175#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000)
176
177/* Video Engine */
178#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000)
179
180#endif
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e84c78c2a8b7
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-dove/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Dove platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <mach/bridge-regs.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29
30 @ if no low interrupts set, check high interrupts
31 ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
32 ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 moveq \irqnr, #63
34 andeqs \irqstat, \irqstat, \tmp
35
36 @ find first active interrupt source
37 clzne \irqstat, \irqstat
38 subne \irqnr, \irqnr, \irqstat
39 .endm
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
new file mode 100644
index 000000000000..0ee70ff39e11
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-dove/include/mach/gpio.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <asm/errno.h>
13#include <mach/irqs.h>
14#include <plat/gpio.h>
15#include <asm-generic/gpio.h> /* cansleep wrappers */
16
17#define GPIO_MAX 64
18
19#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
20#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
21
22#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
23
24#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
25#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
26#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
27#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
28#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
29#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
30#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
31#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)
32
33static inline int gpio_to_irq(int pin)
34{
35 if (pin < NR_GPIO_IRQS)
36 return pin + IRQ_DOVE_GPIO_START;
37
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(int irq)
42{
43 if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
44 return irq - IRQ_DOVE_GPIO_START;
45
46 return -EINVAL;
47}
48
49#endif
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h
new file mode 100644
index 000000000000..32b0826e7873
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/hardware.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-dove/include/mach/hardware.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "dove.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x1000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE
19
20
21/* Macros below are required for compatibility with PXA AC'97 driver. */
22#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
23 DOVE_SB_REGS_VIRT_BASE)))
24#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
25 DOVE_SB_REGS_PHYS_BASE)
26#endif
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
new file mode 100644
index 000000000000..3b3e4721ce2e
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-dove/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "dove.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
17 DOVE_PCIE0_IO_VIRT_BASE))
18#define __mem_pci(a) (a)
19
20#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
new file mode 100644
index 000000000000..46681466f92b
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -0,0 +1,101 @@
1/*
2 * arch/arm/mach-dove/include/mach/irqs.h
3 *
4 * IRQ definitions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14/*
15 * Dove Low Interrupt Controller
16 */
17#define IRQ_DOVE_BRIDGE 0
18#define IRQ_DOVE_H2C 1
19#define IRQ_DOVE_C2H 2
20#define IRQ_DOVE_NAND 3
21#define IRQ_DOVE_PDMA 4
22#define IRQ_DOVE_SPI1 5
23#define IRQ_DOVE_SPI0 6
24#define IRQ_DOVE_UART_0 7
25#define IRQ_DOVE_UART_1 8
26#define IRQ_DOVE_UART_2 9
27#define IRQ_DOVE_UART_3 10
28#define IRQ_DOVE_I2C 11
29#define IRQ_DOVE_GPIO_0_7 12
30#define IRQ_DOVE_GPIO_8_15 13
31#define IRQ_DOVE_GPIO_16_23 14
32#define IRQ_DOVE_PCIE0_ERR 15
33#define IRQ_DOVE_PCIE0 16
34#define IRQ_DOVE_PCIE1_ERR 17
35#define IRQ_DOVE_PCIE1 18
36#define IRQ_DOVE_I2S0 19
37#define IRQ_DOVE_I2S0_ERR 20
38#define IRQ_DOVE_I2S1 21
39#define IRQ_DOVE_I2S1_ERR 22
40#define IRQ_DOVE_USB_ERR 23
41#define IRQ_DOVE_USB0 24
42#define IRQ_DOVE_USB1 25
43#define IRQ_DOVE_GE00_RX 26
44#define IRQ_DOVE_GE00_TX 27
45#define IRQ_DOVE_GE00_MISC 28
46#define IRQ_DOVE_GE00_SUM 29
47#define IRQ_DOVE_GE00_ERR 30
48#define IRQ_DOVE_CRYPTO 31
49
50/*
51 * Dove High Interrupt Controller
52 */
53#define IRQ_DOVE_AC97 32
54#define IRQ_DOVE_PMU 33
55#define IRQ_DOVE_CAM 34
56#define IRQ_DOVE_SDIO0 35
57#define IRQ_DOVE_SDIO1 36
58#define IRQ_DOVE_SDIO0_WAKEUP 37
59#define IRQ_DOVE_SDIO1_WAKEUP 38
60#define IRQ_DOVE_XOR_00 39
61#define IRQ_DOVE_XOR_01 40
62#define IRQ_DOVE_XOR0_ERR 41
63#define IRQ_DOVE_XOR_10 42
64#define IRQ_DOVE_XOR_11 43
65#define IRQ_DOVE_XOR1_ERR 44
66#define IRQ_DOVE_LCD_DCON 45
67#define IRQ_DOVE_LCD1 46
68#define IRQ_DOVE_LCD0 47
69#define IRQ_DOVE_GPU 48
70#define IRQ_DOVE_PERFORM_MNTR 49
71#define IRQ_DOVE_VPRO_DMA1 51
72#define IRQ_DOVE_SSP_TIMER 54
73#define IRQ_DOVE_SSP 55
74#define IRQ_DOVE_MC_L2_ERR 56
75#define IRQ_DOVE_CRYPTO_ERR 59
76#define IRQ_DOVE_GPIO_24_31 60
77#define IRQ_DOVE_HIGH_GPIO 61
78#define IRQ_DOVE_SATA 62
79
80/*
81 * DOVE General Purpose Pins
82 */
83#define IRQ_DOVE_GPIO_START 64
84#define NR_GPIO_IRQS 64
85
86/*
87 * PMU interrupts
88 */
89#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
90#define NR_PMU_IRQS 7
91#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
92
93#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
94
95/* Required for compatability with PXA AC97 driver. */
96#define IRQ_AC97 IRQ_DOVE_AC97
97/* Required for compatability with PXA DMA driver. */
98#define IRQ_DMA IRQ_DOVE_PDMA
99/* Required for compatability with PXA NAND driver */
100#define IRQ_NAND IRQ_DOVE_NAND
101#endif
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
new file mode 100644
index 000000000000..d66872074946
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/memory.h
@@ -0,0 +1,10 @@
1/*
2 * arch/arm/mach-dove/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
new file mode 100644
index 000000000000..3ad9f946a9e8
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -0,0 +1,54 @@
1/*
2 * arch/arm/mach-dove/include/mach/pm.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_PM_H
10#define __ASM_ARCH_PM_H
11
12#include <asm/errno.h>
13#include <mach/irqs.h>
14
15#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16#define CLOCK_GATING_USB0_MASK (1 << 0)
17#define CLOCK_GATING_USB1_MASK (1 << 1)
18#define CLOCK_GATING_GBE_MASK (1 << 2)
19#define CLOCK_GATING_SATA_MASK (1 << 3)
20#define CLOCK_GATING_PCIE0_MASK (1 << 4)
21#define CLOCK_GATING_PCIE1_MASK (1 << 5)
22#define CLOCK_GATING_SDIO0_MASK (1 << 8)
23#define CLOCK_GATING_SDIO1_MASK (1 << 9)
24#define CLOCK_GATING_NAND_MASK (1 << 10)
25#define CLOCK_GATING_CAMERA_MASK (1 << 11)
26#define CLOCK_GATING_I2S0_MASK (1 << 12)
27#define CLOCK_GATING_I2S1_MASK (1 << 13)
28#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
29#define CLOCK_GATING_AC97_MASK (1 << 21)
30#define CLOCK_GATING_PDMA_MASK (1 << 22)
31#define CLOCK_GATING_XOR0_MASK (1 << 23)
32#define CLOCK_GATING_XOR1_MASK (1 << 24)
33#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
34
35#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
36#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
37
38static inline int pmu_to_irq(int pin)
39{
40 if (pin < NR_PMU_IRQS)
41 return pin + IRQ_DOVE_PMU_START;
42
43 return -EINVAL;
44}
45
46static inline int irq_to_pmu(int irq)
47{
48 if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
49 return irq - IRQ_DOVE_PMU_START;
50
51 return -EINVAL;
52}
53
54#endif
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
new file mode 100644
index 000000000000..356afda56853
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/system.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-dove/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <mach/bridge-regs.h>
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19static inline void arch_reset(char mode, const char *cmd)
20{
21 /*
22 * Enable soft reset to assert RSTOUTn.
23 */
24 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
25
26 /*
27 * Assert soft reset.
28 */
29 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
30
31 while (1)
32 ;
33}
34
35
36#endif
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h
new file mode 100644
index 000000000000..251d538541db
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/timex.h
@@ -0,0 +1,9 @@
1/*
2 * arch/arm/mach-dove/include/mach/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
new file mode 100644
index 000000000000..2c5cdd7a3eed
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-dove/include/mach/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <mach/dove.h>
10
11#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
12#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
13
14#define LSR_THRE 0x20
15
16static void putc(const char c)
17{
18 int i;
19
20 for (i = 0; i < 0x1000; i++) {
21 /* Transmit fifo not full? */
22 if (*UART_LSR & LSR_THRE)
23 break;
24 }
25
26 *UART_THR = c;
27}
28
29static void flush(void)
30{
31}
32
33/*
34 * nothing to do
35 */
36#define arch_decomp_setup()
37#define arch_decomp_wdog()
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8b2c974755c6
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-dove/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfd800000
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
new file mode 100644
index 000000000000..61bfcb3b08c2
--- /dev/null
+++ b/arch/arm/mach-dove/irq.c
@@ -0,0 +1,133 @@
1/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
21#include "common.h"
22
23static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
24{
25 int irqoff;
26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
27
28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
29 3 + irq - IRQ_DOVE_GPIO_24_31;
30
31 orion_gpio_irq_handler(irqoff << 3);
32 if (irq == IRQ_DOVE_HIGH_GPIO) {
33 orion_gpio_irq_handler(40);
34 orion_gpio_irq_handler(48);
35 orion_gpio_irq_handler(56);
36 }
37}
38
39static void pmu_irq_mask(unsigned int irq)
40{
41 int pin = irq_to_pmu(irq);
42 u32 u;
43
44 u = readl(PMU_INTERRUPT_MASK);
45 u &= ~(1 << (pin & 31));
46 writel(u, PMU_INTERRUPT_MASK);
47}
48
49static void pmu_irq_unmask(unsigned int irq)
50{
51 int pin = irq_to_pmu(irq);
52 u32 u;
53
54 u = readl(PMU_INTERRUPT_MASK);
55 u |= 1 << (pin & 31);
56 writel(u, PMU_INTERRUPT_MASK);
57}
58
59static void pmu_irq_ack(unsigned int irq)
60{
61 int pin = irq_to_pmu(irq);
62 u32 u;
63
64 u = ~(1 << (pin & 31));
65 writel(u, PMU_INTERRUPT_CAUSE);
66}
67
68static struct irq_chip pmu_irq_chip = {
69 .name = "pmu_irq",
70 .mask = pmu_irq_mask,
71 .unmask = pmu_irq_unmask,
72 .ack = pmu_irq_ack,
73};
74
75static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
76{
77 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
78
79 cause &= readl(PMU_INTERRUPT_MASK);
80 if (cause == 0) {
81 do_bad_IRQ(irq, desc);
82 return;
83 }
84
85 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
86 if (!(cause & (1 << irq)))
87 continue;
88 irq = pmu_to_irq(irq);
89 desc = irq_desc + irq;
90 desc_handle_irq(irq, desc);
91 }
92}
93
94void __init dove_init_irq(void)
95{
96 int i;
97
98 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
99 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
100
101 /*
102 * Mask and clear GPIO IRQ interrupts.
103 */
104 writel(0, GPIO_LEVEL_MASK(0));
105 writel(0, GPIO_EDGE_MASK(0));
106 writel(0, GPIO_EDGE_CAUSE(0));
107
108 /*
109 * Mask and clear PMU interrupts
110 */
111 writel(0, PMU_INTERRUPT_MASK);
112 writel(0, PMU_INTERRUPT_CAUSE);
113
114 for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
115 set_irq_chip(i, &orion_gpio_irq_chip);
116 set_irq_handler(i, handle_level_irq);
117 irq_desc[i].status |= IRQ_LEVEL;
118 set_irq_flags(i, IRQF_VALID);
119 }
120 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
121 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
122 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
123 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
124 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
125
126 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
127 set_irq_chip(i, &pmu_irq_chip);
128 set_irq_handler(i, handle_level_irq);
129 irq_desc[i].status |= IRQ_LEVEL;
130 set_irq_flags(i, IRQF_VALID);
131 }
132 set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
133}
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
new file mode 100644
index 000000000000..502d1ca2f4b7
--- /dev/null
+++ b/arch/arm/mach-dove/pcie.c
@@ -0,0 +1,238 @@
1/*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include <asm/delay.h>
18#include <plat/pcie.h>
19#include <mach/irqs.h>
20#include <mach/bridge-regs.h>
21#include "common.h"
22
23struct pcie_port {
24 u8 index;
25 u8 root_bus_nr;
26 void __iomem *base;
27 spinlock_t conf_lock;
28 char io_space_name[16];
29 char mem_space_name[16];
30 struct resource res[2];
31};
32
33static struct pcie_port pcie_port[2];
34static int num_pcie_ports;
35
36
37static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
38{
39 struct pcie_port *pp;
40
41 if (nr >= num_pcie_ports)
42 return 0;
43
44 pp = &pcie_port[nr];
45 pp->root_bus_nr = sys->busnr;
46
47 /*
48 * Generic PCIe unit setup.
49 */
50 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
51
52 orion_pcie_setup(pp->base, &dove_mbus_dram_info);
53
54 /*
55 * IORESOURCE_IO
56 */
57 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
58 "PCIe %d I/O", pp->index);
59 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
60 pp->res[0].name = pp->io_space_name;
61 if (pp->index == 0) {
62 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
63 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
64 } else {
65 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
66 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
67 }
68 pp->res[0].flags = IORESOURCE_IO;
69 if (request_resource(&ioport_resource, &pp->res[0]))
70 panic("Request PCIe IO resource failed\n");
71 sys->resource[0] = &pp->res[0];
72
73 /*
74 * IORESOURCE_MEM
75 */
76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
77 "PCIe %d MEM", pp->index);
78 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
79 pp->res[1].name = pp->mem_space_name;
80 if (pp->index == 0) {
81 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
82 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
83 } else {
84 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
85 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
86 }
87 pp->res[1].flags = IORESOURCE_MEM;
88 if (request_resource(&iomem_resource, &pp->res[1]))
89 panic("Request PCIe Memory resource failed\n");
90 sys->resource[1] = &pp->res[1];
91
92 sys->resource[2] = NULL;
93
94 return 1;
95}
96
97static struct pcie_port *bus_to_port(int bus)
98{
99 int i;
100
101 for (i = num_pcie_ports - 1; i >= 0; i--) {
102 int rbus = pcie_port[i].root_bus_nr;
103 if (rbus != -1 && rbus <= bus)
104 break;
105 }
106
107 return i >= 0 ? pcie_port + i : NULL;
108}
109
110static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
111{
112 /*
113 * Don't go out when trying to access nonexisting devices
114 * on the local bus.
115 */
116 if (bus == pp->root_bus_nr && dev > 1)
117 return 0;
118
119 return 1;
120}
121
122static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
123 int size, u32 *val)
124{
125 struct pcie_port *pp = bus_to_port(bus->number);
126 unsigned long flags;
127 int ret;
128
129 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
130 *val = 0xffffffff;
131 return PCIBIOS_DEVICE_NOT_FOUND;
132 }
133
134 spin_lock_irqsave(&pp->conf_lock, flags);
135 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
136 spin_unlock_irqrestore(&pp->conf_lock, flags);
137
138 return ret;
139}
140
141static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
142 int where, int size, u32 val)
143{
144 struct pcie_port *pp = bus_to_port(bus->number);
145 unsigned long flags;
146 int ret;
147
148 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
149 return PCIBIOS_DEVICE_NOT_FOUND;
150
151 spin_lock_irqsave(&pp->conf_lock, flags);
152 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
153 spin_unlock_irqrestore(&pp->conf_lock, flags);
154
155 return ret;
156}
157
158static struct pci_ops pcie_ops = {
159 .read = pcie_rd_conf,
160 .write = pcie_wr_conf,
161};
162
163static void __devinit rc_pci_fixup(struct pci_dev *dev)
164{
165 /*
166 * Prevent enumeration of root complex.
167 */
168 if (dev->bus->parent == NULL && dev->devfn == 0) {
169 int i;
170
171 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
172 dev->resource[i].start = 0;
173 dev->resource[i].end = 0;
174 dev->resource[i].flags = 0;
175 }
176 }
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
179
180static struct pci_bus __init *
181dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
182{
183 struct pci_bus *bus;
184
185 if (nr < num_pcie_ports) {
186 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
187 } else {
188 bus = NULL;
189 BUG();
190 }
191
192 return bus;
193}
194
195static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
196{
197 struct pcie_port *pp = bus_to_port(dev->bus->number);
198
199 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
200}
201
202static struct hw_pci dove_pci __initdata = {
203 .nr_controllers = 2,
204 .swizzle = pci_std_swizzle,
205 .setup = dove_pcie_setup,
206 .scan = dove_pcie_scan_bus,
207 .map_irq = dove_pcie_map_irq,
208};
209
210static void __init add_pcie_port(int index, unsigned long base)
211{
212 printk(KERN_INFO "Dove PCIe port %d: ", index);
213
214 if (orion_pcie_link_up((void __iomem *)base)) {
215 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
216
217 printk(KERN_INFO "link up\n");
218
219 pp->index = index;
220 pp->root_bus_nr = -1;
221 pp->base = (void __iomem *)base;
222 spin_lock_init(&pp->conf_lock);
223 memset(pp->res, 0, sizeof(pp->res));
224 } else {
225 printk(KERN_INFO "link down, ignoring\n");
226 }
227}
228
229void __init dove_pcie_init(int init_port0, int init_port1)
230{
231 if (init_port0)
232 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
233
234 if (init_port1)
235 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
236
237 pci_common_init(&dove_pci);
238}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-26 22:30:48 -0400